- 您現在的位置：買賣IC網 > PDF目錄98249 > TLV1571CDWRG4 (TEXAS INSTRUMENTS INC) 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 PDF資料下載
參數資料
| 型號： | TLV1571CDWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOP-24 |
| 文件頁數： | 6/36頁 |
| 文件大小： | 545K |
| 代理商： | TLV1571CDWRG4 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
software START conversion (continued)
system clock source
The TLV1571/TLV1578 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used
for most conversion subtasks. The source of SYSCLK is programmable via control register zero bit 5. The
source of SYSCLK is changed at the rising edge of WR of the cycle when CR0.D5 is programmed.
internal clock (CR0.D5 = 0, SYSCLK = internal OSC)
The TLV1571/TLV1578 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of
SYSCLK, the internal clock starts with a delay (one half of the OSC period max) after the falling edge of the
conversion trigger (either WR, RD, or CSTART). The OSC speed can be set to 10
± 1 MHz or 20 ± 2 MHz by
setting register bit CR1.6.
external clock (CR0.D5 = 1, SYSCLK = external clock)
The TLV1571/TLV1578 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from
1 MHz to 20 MHz.
host processor interface
The TLV1571/TLV1578 provides a generic high-speed parallel interface that is compatible with
high-performance DSPs and general-purpose microprocessors. The interface includes D(0–9), INT/EOC, RD,
and WR.
output format
The data output format is unipolar (code 0 to 1023) when the device is operated in single-ended input mode.
The output code format can be either binary or twos complement by setting register bit CR1.D3.
power up and initialization
After power up, CS must be low to begin an I/O cycle. INT/EOC is initially high. The TLV1571/TLV1578 requires
two write cycles to configure the two control registers. The first conversion after the device has returned from
the power-down state may be invalid and should be disregarded.
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than
±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV1572CD | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV1572CDRG4 | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV1572ID | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV1572CDG4 | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV1572IDR | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV1571CPW | 制造商:Rochester Electronics LLC 功能描述:10 BIT, 1.2 MSPS, PARALLEL ADC, 1/8 CHAN - Bulk |
| TLV1571IDW | 功能描述:模數轉換器 - ADC 10bit 1.2 MSPS PA RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1571IDWG4 | 功能描述:模數轉換器 - ADC 10bit 1.2 MSPS PA RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1571IPW | 功能描述:模數轉換器 - ADC 10bit 1.2 MSPS PA RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV1571IPWG4 | 功能描述:模數轉換器 - ADC 1-Ch 10-Bit 1.25MSPS 8-Ch DSP/SPI RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發布緊急采購，3分鐘左右您將得到回復。