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參數資料
| 型號： | TLV1571IPWLE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 文件頁數： | 8/26頁 |
| 文件大小： | 388K |
| 代理商： | TLV1571IPWLE |
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170A –MARCH 1999 – REVISED AUGUST 1999
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
simplified analog input analysis
Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
The capacitance charging voltage is given by:
Where
Rt = Rs + Ri
Ri = Ri(ADC) + Ri(MUX)
tch = Charge time
V
C(t) +
V
S
1–e
–t
ch
RtCi
The input impedance Ri is 718 at 5 V, and is higher (~ 1.25 k) at 2.7 V. The final voltage to 1/2 LSB is given
by:
VC (1/2 LSB) = VS – (VS/2048)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1/2 LSB) = Rt × Ci × ln(2048)
V
S *
V
S
2048
+ V
S
1–e
–t
ch
RtCi
Where
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 718 ) × 15 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
tch (1/2 LSB) ≤ 6x 1/f(SCLK)
Therefore the maximum SCLK frequency is:
Max(f(SCLK)) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)
(1)
(2)
(3)
(4)
(5)
(6)
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| TLV1572CDRG4 | 功能描述:模數轉換器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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