- 您現在的位置：買賣IC網 > PDF目錄98251 > TLV2548QDWREP (TEXAS INSTRUMENTS INC) 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 PDF資料下載
參數資料
| 型號： | TLV2548QDWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數： | 42/42頁 |
| 文件大小： | 977K |
| 代理商： | TLV2548QDWREP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當前第42頁
TLV2544Q, TLV2548Q, TLV2548M
3V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER
SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN
SGLS119F FEBRUARY 2002 REVISED OCTOBER 2009
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TLV2544/TLV2548 conversion modes
The TLV2544 and TLV2548 have four different conversion modes (mode 00, 01, 10, 11). The operation of each
mode is slightly different, depending on how the converter performs the sampling and which host interface is
used. The trigger for a conversion can be an active CSTART (extended sampling), CS (normal sampling, SPI
interface), or FS (normal sampling, TMS320 DSP interface). When FS is used as the trigger, CS can be held
active, i.e. CS does not need to be toggled through the trigger sequence. SDI can be one of the channel select
commands, such as SELECT CHANNEL 0. Different types of triggers should not be mixed throughout the repeat
and sweep operations. When CSTART is used as the trigger, the conversion starts on the rising edge of
CSTART. The minimum low time for CSTART is equal to t(SAMPLE). If an active CS or FS is used as the trigger,
the conversion is started after the 16th or 28th SCLK edge. Enough time (for conversion) should be allowed
between consecutive triggers so that no conversion is terminated prematurely.
one shot mode (mode 00)
One shot mode (mode 00) does not use the FIFO, and the EOC is generated as the conversion is in progress
(or INT is generated after the conversion is done).
repeat mode (mode 01)
Repeat mode (mode 01) uses the FIFO. This mode setup requires configuration cycle and channel select cycle.
Once the programmed FIFO threshold is reached, the FIFO must be read, or the data is lost when the sequence
starts over again with the SELECT cycle and series of triggers. No configuration is required except for
reselecting the channel unless the operation mode is changed. This allows the host to set up the converter and
continue monitoring a fixed input and come back to get a set of samples when preferred.
Triggered by CSTART: The first conversion can be started with a select cycle or CSTART. To do so, the user
can issue CSTART during the select cycle, immediately after the four-bit channel select command. The first
sample started as soon as the select cycle is finished (i.e., CS returns to 1). If there is enough time (2
s) left
between the SELECT cycle and the following CSTART, a conversion is carried out. In this case, you will need
one less trigger to fill the FIFO. Succeeding samples are triggered by CSTART.
sweep mode (mode 10)
Sweep mode (mode 10) also uses the FIFO. Once it is programmed in this mode, all of the channels listed in
the selected sweep sequence are visited in sequence. The results are converted and stored in the FIFO. This
sweep sequence may not be completed if the FIFO threshold is reached before the list is completed. This allows
the system designer to change the sweep sequence length. Once the FIFO has reached its programmed
threshold, an interrupt (INT) is generated. The host must issue a read FIFO command to read and clear the FIFO
before the next sweep can start.
repeat sweep mode (mode 11)
Repeat sweep mode (mode 11) works the same way as mode 10 except the operation has an option to continue
even if the FIFO threshold is reached. Once the FIFO has reached its programmed threshold, an interrupt (INT)
is generated. Then two things may happen:
1.
The host may choose to act on it (read the FIFO) or ignore it. If the next cycle is a read FIFO cycle, all of
the data stored in the FIFO is retained until it has been read in order.
2.
If the next cycle is not a read FIFO cycle, or another CSTART is generated, all of the content stored in the
FIFO is cleared before the next conversion result is stored in the FIFO, and the sweep is continued.
相關PDF資料 |
PDF描述 |
|---|---|
| TLV2545IDGKRG4 | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2545CDGKRG4 | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2545IDRG4 | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| TLV2548CDWR | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2548CPW | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TLV2548QDWRG4 | 功能描述:模數轉換器 - ADC Auto Cat 12B 200 kSPS ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2553EVM | 功能描述:數據轉換 IC 開發工具 TLV2553 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| TLV2553EVM-PDK | 功能描述:TLV2553 - 12 Bit 200k Samples per Second Analog to Digital Converter (ADC) Evaluation Board 制造商:texas instruments 系列:- 零件狀態:有效 A/D 轉換器數:1 位數:12 采樣率（每秒）:200k 數據接口:SPI 輸入范圍:0 ~ VREF 不同條件下的功率（典型值）:- 使用的 IC/零件:TLV2553 所含物品:板 標準包裝:1 |
| TLV2553IDW | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2553IDWG4 | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發布緊急采購，3分鐘左右您將得到回復。