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參數資料
| 型號： | TLV2553IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數： | 13/29頁 |
| 文件大小： | 603K |
| 代理商： | TLV2553IPWRG4 |
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TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
20
www.ti.com
PRINCIPLES OF OPERATION
detailed description
Initially, with chip select (CS) high, I/O CLOCK and DATA IN are disabled and DATA OUT is in the
high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA IN and
removes DATA OUT from the high-impedance state. The input data is an 8–bit data stream consisting of a 4-bit
address or command (D7–D4) and a 4-bit configuration data (D3–D0). Configuration register 1, CFGR1, which
controls output data format configuration, consists of a 2-bit data length select (D3–D2), an output MSB or LSB
first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to any command (from DATA IN)
except for command 1111b. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data
to the input data register. During this transfer, the I/O CLOCK sequence also shifts the previous conversion
result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock
cycles long depending on the data-length selection in the input data register. Sampling of the analog input
begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the
I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the
conversion.
converter operation
The operation of the converter is organized as a succession of three distinct cycles: 1) the data I/O cycle, 2)
the sampling cycle and 3) the conversion cycle. The first two are partially overlapped.
data I/O cycle
The data I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods,
depending on the selected output data length. During the I/O cycle, the following two operations take place
simultaneously. An 8-bit data stream consisting of address/command and configuration information is provided
to DATA IN. This data is shifted into the device on the rising edge of the first eight I/O CLOCK clocks. DATA
INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers. The data output, with a length
of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on
the rising edge of EOC. When CS is toggled between conversions, the first output data bit occurs on the falling
edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each
succeeding bit is clocked out on the falling edge of each succeeding I/O CLOCK.
sampling cycle
During the sampling cycle, one of the analog inputs is internally connected to the capacitor array of the converter
to store the analog input signal. The converter starts sampling the selected input immediately after the four
address/command bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection.
After the 8-bit data stream has been clocked in, DATA IN should be held at a fixed digital level until EOC goes
high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence
of external digital noise.
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相關代理商/技術參數 |
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| TLV2553IPWRQ1 | 功能描述:12 Bit Analog to Digital Converter 11 Input 1 SAR 20-TSSOP 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態:有效 位數:12 采樣率（每秒）:200k 輸入數:11 輸入類型:單端 數據接口:SPI 配置:MUX-S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉換器數:1 架構:SAR 參考類型:外部 電壓 - 電源，模擬:2.7 V ~ 5.5 V 電壓 - 電源，數字:2.7 V ~ 5.5 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商器件封裝:20-TSSOP 標準包裝:1 |
| TLV2556EVM | 功能描述:數據轉換 IC 開發工具 TLV2556 Eval Mod RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| TLV2556IDW | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IDWG4 | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| TLV2556IDWR | 功能描述:模數轉換器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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