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參數(shù)資料
| 型號(hào)： | TLV2556MPWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁(yè)數(shù)： | 26/37頁(yè) |
| 文件大?。?/td> | 705K |
| 代理商： | TLV2556MPWREP |
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Power-Down Features
Analog Multiplexer
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough
before the end of the current conversion cycle, the previous conversion result is saved in the internal output
buffer and shifted out during the next I/O cycle.
When CS is held low continuously for multiple cycles, the first data bit of the newly completed conversion occurs
on DATA OUT on the rising edge of EOC or falling edge of INT. Note that the first cycle in the series still requires
a transition of CS from high to low. When a new conversion is started after the last falling edge of I/O CLOCK,
EOC goes low and the serial output is forced low until EOC goes high again.
When CS is toggled between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On
each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in
the serial conversion result until the required number of bits has been output.
When command (D7–D4) 1110b is clocked into the input data register during the first four I/O CLOCK cycles, the
software power-down mode is selected. Software power down is activated on the falling edge of the fourth I/O
CLOCK pulse.
During software power down, all internal circuitry is put in a low-current standby mode. The internal reference (if
being used) is powered down. No conversion is performed. The internal output buffer keeps the previous
conversion cycle data results provided that all digital inputs are held above VCC – 0.5 V or below 0.5 V. The I/O
logic remains active so the current I/O cycle must be completed even when the power-down mode is selected.
Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The
device remains in the software power-down mode until a valid input address (other than command 1110b) is
clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out
during the next I/O cycle. If using the internal reference, care must be taken to allow the reference to power on
completely before a valid conversion can be performed. It requires 1 ms to resume from a software power down.
The ADC also has an auto power-down mode. This is transparent to users. The ADC goes into auto power down
within one I/O CLOCK cycle after the conversion is complete and resumes, with a small delay after an active CS
is sent to the ADC. This mode keeps built-in reference so resumption is fast enough to be used between cycles.
The 11 analog inputs, three internal voltages, and power-down mode are selected by the input multiplexer
according to the input addresses shown in Table 2. The input multiplexer is a break-before-make type to reduce
input-to-input noise rejection resulting from channel switching. Sampling of the analog inputs starts on the falling
edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the
falling edge of the last I/O CLOCK pulse. The three internal test inputs are applied to the multiplexer, then
sampled and converted in the same manner as the external analog inputs. The first conversion after the device
has returned from the power-down state may not read accurately due to internal device settling.
32
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2556-EP
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