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參數資料
| 型號： | TLV2556MPWREP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數： | 36/37頁 |
| 文件大小： | 705K |
| 代理商： | TLV2556MPWREP |
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TIMING CHARACTERISTICS
(1)
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
operating characteristics, VREF+ = 5 V, SCLK frequency = 15 MHz, VCC = 5 V, load = 25 pF, TA= -40°C to 85°C (unless
otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
tw1
Pulse duration I/O CLOCK high or low
26.7
100000
ns
tsu1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38)
12
ns
th1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38)
0
ns
tsu2
25
ns
th2
Hold time CS pulse duration high time (see Figure 39)
100
ns
th3
Hold time CS low after last I/O CLOCK falling edge (see Figure 39)
0
ns
th4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40)
2
ns
th5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43)
0
ns
th6
Hold time CS high after INT falling edge (see Figure 43)
0
ns
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
th7
10
ns
low (see Figure 44)
Load = 25 pF
28
Delay time CS falling edge to DATA OUT valid
td1
ns
(MSB or LSB) (see Figure 37)
Load = 10 pF
20
td2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37)
10
ns
td3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40)
2
20
ns
td4
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41)
55
ns
td5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion
1.5
s
td6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41)
MAX(tconv)
ns
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
td7
4
ns
(see Figure 42)
td9
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44)
1
28
ns
tt1
1
s
tt2
Transition time DATA OUT (see Figure 40)
5
ns
tt3
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42)
2.4
ns
tt4
Transition time DATA IN, CS
10
s
MAX(tconv) +
tcyc
Total cycle time (sample, conversion and delays)(2)
I/O period
s
(8/12/16 CLKs)
Source impedance = 25
600
Source impedance = 100
650
tsample
Channel acquisition time (sample), at 1 k
(2)
ns
Source impedance = 500
700
Source impedance = 1 k
1000
(1)
Timing parameters are not production tested.
(2)
I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
8
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TLV2556-EP
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