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參數資料
| 型號： | TLV320AIC10CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 13/57頁 |
| 文件大小： | 454K |
| 代理商： | TLV320AIC10CPFB |
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2–6
2.2
Reset and Power-Down Functions
2.2.1
Software and Hardware Reset
The TLV320AIC10 resets the internal counters and registers in response to either of two events:
A low-going reset pulse is applied to terminal RESET
A 1 is written to the programmable-software reset bit (D3 of control register 1)
Either event resets the control registers and clears all the sequential circuits in the device. Reset signals should be
at least six master-clock periods long. It is recommended to synchronize the reset signal with the master clock in
master/slave cascade, and to tie all reset pins together. For devices in cascade, it takes at least two FS cycles to apply
software reset to all devices, with the master being always programmed last.
2.2.2
Software and Hardware Power Down
With the exception of the digital interface, the device enters the power-down mode when D1 and D2 in control register
3 are set to 1. When PWRDWN is taken low, the entire device is powered down. In either case, the register contents
are preserved and the output of the monitor amplifier is held at the midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than it is during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs. Figure 2–7 represents the internal power-down logic.
PWRDWN
Software Power Down
(For Control Register 3, D1 & D2)
D1 and D2 Are
Programmed Through a
Secondary Write
Operation
Internal TLV320AIC10
Figure 2–7. Internal Power-Down Logic
2.2.2.1 Software Power Down
When D1 and D2 of control register 3 are set to 1, TLV320AIC10 enters the software power-down mode. In this state,
the digital-interface circuit is still active, while the internal ADC and DAC channels and differential outputs OUTP and
OUTM are disabled, and DOUT and FSD are inactive. Register data in secondary serial communications is still
accepted, but data in primary serial communications is ignored. The device returns to normal operation when D1 and
D2 of control register 3 are reset.
2.2.2.2 Hardware Power Down
When PWRDWN is held low, the device enters the hardware power-down mode. In this state, the internal-clock
control circuit and the differential outputs OUTP and OUTM are disabled. All other digital I/Os are either disabled, or
remain in the same state they were in immediately before power down. DIN can not accept any data input. The device
can only be returned to normal operation by taking and holding PWRDWN high. When not holding the device in the
hardware power-down mode, PWRDWN should be tied high.
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