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參數資料
| 型號： | TLV320AIC10CPFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 17/57頁 |
| 文件大小： | 454K |
| 代理商： | TLV320AIC10CPFB |
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2–10
2.7.4
Frame-Sync (FS) Function—Slave Mode
The slave mode is selected by connecting pin M/S to LO. The frame-sync timing is generated externally by the master,
as shown in Figure 2–13 (that is, FSD) and is applied to FS of the slave to control the ADC and DAC timing.
MP
32 SCLKs
FSD (Master)
to FS (Slave)
FS
(Master to DSP)
SP
MS
SS
MP
NOTE: MP: master primary (master-device data is transferred during this period, the DOUT of the slave device is in high-impedance state).
SP: slave primary (slave device data is transferred during this period, the DOUT of master device is in high-impedance state).
MS: master secondary (master device control register information is transferred during this period, the DOUT of slave device is in high-
impedance state).
SS: slave secondary (slave device control register information is transferred during this period, the DOUT of master device is in high-
impedance state).
Figure 2–13. Master Device’s FS Output to DSP and FSD Output to the Slave
2.7.5
Frame-Sync Delayed (FSD) Function, Cascade Mode
In cascade mode, the DSP must be able to identify the master and slaves according to the register map shown in
Appendix A. Each device in the cascade contains a 3-bit cascade register (D15-D13 in the register address) that has
been programmed by the ACD (automatic cascade detection) with an address value equal to its position in the
cascade during the device’s power-up initialization (see Appendix A). The device address of the master is always
equal to the number of slaves in the cascade. For example, in Figure 2–14, D15-D13 of the master is 011, as shown
in row 4 of Table A-1 (Appendix A). The DSP receives all frame-sync pulses from the master though the masters FS.
The master FSD is output to the first slave, and the first slave FSD is output to the second slave device, and so on.
Figure 2–14 shows the cascade of 4 TLV320AIC10s in which the closest one to the DSP is the master, and the rest
are slaves. The FSD output of each device is input to the FS terminal of the succeeding device. Figure 2–15 shows
the FSD timing sequence in the cascade.
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
Slave 2
Slave 1
Slave 0
Master
MCLK
DIN
DOUT
FSD
SCLK
FSD
FS
CLKOUT
DX
DR
FSX
FSR
CLKX
CLKR
TMS320C54XX
DVDD
FSD
M/S
(or Master Clock Source)
DVDD
1 k
Figure 2–14. Cascade Mode Connection (to DSP Interface)
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