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參數資料
型號: TLV320AIC10IGQER
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝: MICRO, PLASTIC, BGA-80
文件頁數: 11/57頁
文件大小: 454K
代理商: TLV320AIC10IGQER
2–5
2.1.10 Analog and Digital Loopback
The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used
for in-circuit system level tests. The analog loopback routes the DAC low-pass filter output into the analog input where
it is then converted by the ADC to a digital word. The digital loopback routes the ADC output to the DAC input on the
device. Analog loopback is enabled by writing 01 to bits D7 and D6 respectively in control register 3. Digital loopback
is enabled by writing 10 to bits D7 and D6 in control register 3 (see Appendix A).
2.1.11 FIR Overflow Flag
The decimator FIR filter sets an overflow flag (bit D7) in control register 1 to indicate that the input analog signal has
exceeded the range of the internal decimation-filter calculations. When the FIR overflow flag has been set in the
register, it remains set until the register is read by the user. Reading this value resets the overflow flag.
If FIR overflow occurs, the input signal has to be attenuated either by the PGA or some other method.
2.1.12 FIR Bypass Mode
An option is provided to bypass the FIR filter sections of the decimation and interpolation filters. This mode is selected
through bit D2 of control register 1, and effectively increases the frequency of the FS and SCLK signals to 4 times
the normal FIR-filter output rate, since the decimation/interpolation factor of the bypassed filter stage is 4. The sinc
filters of the two paths can not be bypassed.
The AIC10 is capable of supporting a maximum of four devices in cascade.
If the FIR filter is bypassed, the signal-to-noise ratio (SNR) is reduced to 69 dB. The FIR bypass mode offers users
the flexibility to implement their own decimation/interpolation FIR filter based on application-specific requirements.
For example users can select this mode to bypass both decimation and interpolation FIR filters and implement a
lower-order FIR filter or an IIR filter externally in the DSP for applications that require group delays smaller than 17/Fs,
which is the AIC10s total group delay.
2.1.13 Low-Power Mode
To select the low-power mode, in which the AIC10 typically consumes 38.6 mW, set bit D7 of control register 2 to 1
and set the sampling rate at 8 ksps.
2.1.14 Event-Monitor Mode
This mode is only available during the register-write cycle, and is enabled by writing 11 to bits D6 and D7 of control
register 3; performing a register read terminates event-monitor mode3. The event monitor mode is provided for
applications that need hardware control and monitoring of external events. By allowing the device to drive the FLAG
terminal (set through bit D3 of the control register 3), the host DSP is capable of system control through the same
serial port that connects the device. Along with this control is the capability of monitoring the value of the ALTIN
terminal during a secondary communication cycle. One application of this function is in monitoring RING DETECT
or OFFHOOK DETECT from a phone-answering system. FLAG allows response to these incoming control signals.
Figure 2–6 shows the timing associated with this operating mode.
FS
DOUT
ALTDI
Primary
Secondary
16 bits
NOTE A: When DIN performs a write operation (sets D12 to 0) during secondary communication.
Figure 2–6. Event Monitor Mode Timing
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