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參數資料
| 型號： | TLV320AIC11IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數： | 15/55頁 |
| 文件大小： | 270K |
| 代理商： | TLV320AIC11IPFBG4 |
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2–8
2.3
Clock Source
MCLK is the external master-clock input. The clock circuit generates and distributes the necessary clocks throughout
the device. When the device is in the master mode, SCLK and FS are output and derived from MCLK in order to
provide clocking of the serial communications between the device and a DSP (digital signal processor). When in the
slave mode, SCLK and FS are all inputs. The SCLK can be connected to a faster clock source to speed up serial
communication between the slave and the master while the internal clock is maintained at 256 clocks per FS period
for internal processing. In SPI mode, the device is a slave and SCLK is connected to the SPICLK source.
2.4
Data Out (DOUT)
DOUT is placed in the high-impedance state after completing transmission of the LSB. In primary communication the
data word is the ADC conversion result. In secondary communication the data in the register read results when
requested by the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are
all zeroes. The state of the master/slave (M/S) terminal is reflected by the MSB in secondary communication (DOUT,
bit D15), and by the LSB in primary communication (DOUT, bit D0).
2.4.1
Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of the master frame-sync (FS).
The most significant data bit then appears first on DOUT.
2.4.2
Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame-sync (FS).
The most significant data bit then appears first on DOUT.
2.5
Data In (DIN)
In a primary communication, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is
used, the LSB (D0) is used to request a secondary communication. In a secondary communication, the data is the
control and configuration data that sets the device for a particular function (see Section 3, Serial Communications).
The LSB of control register 1 determines whether it is a 15-bit or a 16-bit input.
2.6
FC (Hardware Secondary Communication Request)
The FC input provides for hardware requests for secondary communications. FC works in conjunction with the LSB
of the primary data word. FC should be tied low if not used.
2.7
Frame-Sync Function for TLV320AIC11
The frame-sync signal (FS) indicates the device is ready to send or receive data. FS is an output if the M/S pin is
connected to HI (master mode), and an input if the M/S pin is connected to LO (slave mode). The output FSD is a
delay version of the first frame-sync signal (FS) that is output 32 SCLKs after the first FS, and serves as the
frame-sync input to the next slave (see Figure 2–17). The data transferred out of DOUT and into DIN begins on the
falling edge of the FS signal. It can be configured as a frame or as a pulse signal, as determined by pins M0 and M1.
In normal operation, the digital serial interface consists of the shift clock (SCLK), the frame-sync signal (FS), the
ADC-channel data output (DOUT), and the DAC-channel data input (DIN). During the primary frame-synchronization
interval, SCLK clocks the ADC channel results out through DOUT, and clocks 16-bit/(15+1) DAC data in through DIN.
During the secondary frame-synchronization interval, SCLK clocks the register data out through DOUT in normal
operation. If the read bit (D12) is set to 1 and the device transfers control and device parameter in through DOUT.
The timing sequence is shown in Figures 2-1, 2-2, 2-3, and 2-4.
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