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參數資料
| 型號： | TLV320AIC28RGZR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | 7 X 7 MM, PLASTIC, QFN-48 |
| 文件頁數： | 11/85頁 |
| 文件大小： | 1053K |
| 代理商： | TLV320AIC28RGZR |
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TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
19
D Word Select Signals
The word select signal (WCLK) indicates the channel being transmitted:
— WCLK = 0: left channel for I2S mode;
— WCLK = 1: right channel for I2S mode.
For other modes refer to the timing diagrams below.
D Bitclock (BCLK) Signal
In addition to being programmable as master or slave mode, the BCLK can also be configured in two transfer
modes, 256-S transfer mode and continuous transfer mode, which are described below. These modes are
set using bit D12 of control register 06H/page 2.
D 256-S Transfer Mode
In the 256-S mode, the BCLK rate always equals 256 times the WCLK frequency. In the 256-S mode, the
combination of ADC/DAC sampling rate equal to Fsref (as selected by bit D5D0 of control register 00H/page
2) and left-justified mode is not supported. If IOVDD is equal to 1.1 V, then ADC/DAC sampling rate should be
less than 39 kHz for all modes except the left justified mode where it should be less than 24 kHz.
D Continuous Transfer Mode
In the continuous transfer mode, the BCLK rate always equals two-word length times the frequency of
WCLK.
D Right Justified Mode
In right-justified mode, the LSB of left channel is valid on the rising edge of BCLK preceding, the falling edge
on WCLK. Similarly the LSB of right channel is valid on the rising edge of BCLK preceding the rising edge of
WCLK.
BCLK
WCLK
SDIN/
SDOUT
n
n1
1
0
n
n1
1
0
1/fs
LSB
MSB
Left Channel
Right Channel
n2
2
n2
Figure 15. Timing Diagram for Right-Justified Mode
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