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參數(shù)資料
| 型號： | TLV320AIC28RGZR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC48 |
| 封裝： | 7 X 7 MM, PLASTIC, QFN-48 |
| 文件頁數(shù)： | 15/85頁 |
| 文件大小： | 1053K |
| 代理商： | TLV320AIC28RGZR |
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TLV320AIC28
SLAS418B FEBRUARY 2004 REVISED MAY 2005
www.ti.com
22
Fsref
+ MCLK
K
2048
P
P = 1, 2, 3
… 8
K = J.D
J = 1, 2, 3
….63
D = 0, 1, 2
… 9999
P, J and D are register programmable.where J is integer part of K before the decimal point, and D
is four-digit fractional part of K after the decimal point, including lagging zeros.
Examples: If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 7.012, then J = 7, D = 120
The PLL is programmed through Registers 1BH and 1CH of Page 2.
D When PLL is enabled and D = 0, the following conditions must be satisfied
2MHz
v MCLK
P
v 20 MHz
80 MHz
v MCLK
K
P
v 110 MHz
4 v J v 55
D When PLL is enabled D ≠ 0, the following conditions must be satisfied
10 MHz
v MCLK
P
v 20 MHz
80 MHz
v MCLK
K
P
v 110 MHz
4 v J v 11
Example 1:
For MCLK = 12 MHz and Fsref = 44.1 kHz
P = 1, K = 7.5264
J = 7, D = 5264
Example 2:
For MCLK = 12 MHz and Fsref = 48 kHz
P = 1, K = 8.192
J = 8, D = 1920
To externally observe the PLL function, the GPIO2 pin can be set up as the clock monitor (set D2 = 1, register
22h, page 2). Note that besides setting up the PLL and GPIO2, the audio ADC or DAC must be enabled for
the PLL output to appear at the GPIO2.
Example 1:
D Start from power up (with the proper sequence)
D Make sure MCLK is provided and /PWR_DWN and /RESET are both high
D Set and enable PLL
D Connect and power up (do not unmute anything) ADC or DAC or both, for instance:
Page2/Reg03h to C530h or C510h (default is C500h) to connect MICSEL to ADC
Page2/Reg05h to FDFCh (default is FFFCh) to power up ADC.
D Set Page2/Reg22h to 0004h to output PLL to GPIO2 pin.
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