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| 型號(hào)： | TLV320AIC3111IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 93/156頁(yè) |
| 文件大?。?/td> | 1701K |
| 代理商： | TLV320AIC3111IRHBR |
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SLAS644B – JULY 2009 – REVISED OCTOBER 2009
Mode B
To choose mode B, page 0 / register 102, bit D5 must be programmed to 1. In dc-measurement mode B,
a first-order IIR filter is used. The coefficients of this filter are determined by D, page 0 / register 102,
bits D4–D0. The nature of the filter is given in Table 5-23.
Table 5-23. DC Measurement Bandwidth Settings
D: Page 0 / register 102, Bits D4–D0
–3 dB BW (Hz)
–0.5 dB BW (Hz)
1
688,440
236,500
2
275,970
96,334
3
127,400
44,579
4
61,505
21,532
5
30,248
10,590
6
15,004
5,253
7
7,472
2,616
8
3,729
1,305
9
1,862
652
10
931
326
11
465
163
12
232.6
81.5
13
116.3
40.7
14
58.1
20.3
15
29.1
10.2
16
14.54
5.09
17
7.25
2.54
18
3.63
1.27
19
1.8
0.635
20
0.908
0.3165
By programming page 0 / register 103, bit D5 to 1, the averaging filter is periodically reset after 2R number
of ADC_MOD_CLK periods, where R is programmed in page 0 / register 103, bits D4–D0. When page 0 /
register 103, bit D5 is set to 1, then the value of D should be less than the value of R. When page 0 /
register 103, bit D5 is programmed to 0, the averaging filter is never reset.
5.6
Audio DAC and Audio Analog Outputs
Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation
filter, a digital delta-sigma modulator, and an analog reconstruction filter. This high oversampling ratio
(normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization
noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog
outputs include stereo headphone/lineouts and stereo class-D speaker outputs.
5.6.1
DAC
The TLV320AIC3111 stereo audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the
stereo audio DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction
filter. The DAC is designed to provide enhanced performance at low sampling rates through increased
oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
41
Product Folder Link(s): TLV320AIC3111
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TLV320AIC3111IRHBT | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3120 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Mono Audio Codec With Embedded miniDSP and Mono Class-D Speaker Amplifier |
| TLV320AIC3120EVM-U | 功能描述:音頻 IC 開發(fā)工具 TLV320AIC3120EVM-U Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| TLV320AIC3120IRHBR | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3120IRHBT | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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