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參數資料
型號： TLV320AIC33IZQER
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PBGA80
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, VFBGA-80
文件頁數： 47/93頁
文件大小： 1427K
代理商： TLV320AIC33IZQER
www.ti.com ........................................................................................................................................... SLAS480B – JANUARY 2006 – REVISED DECEMBER 2008
Page 0 / Register 17:
MIC3L/R to Left ADC Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D3-D0
R/W
1111
MIC3R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the left ADC PGA
mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to the left ADC PGA
Page 0 / Register 18:
MIC3L/R to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
1111
MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the right ADC PGA
D3–D0
R/W
1111
MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to right ADC PGA
Page 0 / Register 19:
LINE1L to Left ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
Copyright 2006–2008, Texas Instruments Incorporated
51
Product Folder Link(s): TLV320AIC33
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