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參數資料
| 型號： | TLV320AIC36IZQER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA80 |
| 封裝： | 5 X 5 MM, PLASTIC, VFBGA-80 |
| 文件頁數： | 7/168頁 |
| 文件大小： | 1452K |
| 代理商： | TLV320AIC36IZQER |
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SBAS387A – MAY 2009 – REVISED JUNE 2010
www.ti.com
(continued)
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D0
R/W
0
0: Reset DAC miniDSP instruction counter at the start of new frame.
1: Do not reset DAC miniDSP instruction counter at the start of new frame. If DAC miniDSP is used
for Signal Processing
6.2.60 Page 0 / Register 63:
DAC Channel Setup Register 1
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Left DAC Channel Power Control
0: Left DAC Channel Powered Down
1: Left DAC Channel Powered Up
D6
R/W
0
Right DAC Channel Power Control
0: Right DAC Channel Powered Down
1: Right DAC Channel Powered Up
D5–D4
R/W
01
Left DAC Data path Control
00: Left DAC data is disabled
01: Left DAC data Left Channel Audio Interface Data
10: Left DAC data is Right Channel Audio Interface Data
11: Left DAC data is Mono Mix of Left and Right Channel Audio Interface Data
D3–D2
R/W
01
Right DAC Data path Control
00: Right DAC data is disabled
01: Right DAC data Right Channel Audio Interface Data
10: Right DAC data is Left Channel Audio Interface Data
11: Right DAC data is Mono Mix of Left and Right Channel Audio Interface Data
D1–D0
R/W
00
DAC Channel Volume Control's Soft-Step control
00: Soft-Stepping is 1 step per 1 DAC Word Clock
01: Soft-Stepping is 1 step per 2 DAC Word Clocks
10: Soft-Stepping is disabled
11: Reserved. Do not use
6.2.61 Page 0 / Register 64:
DAC Channel Setup Register 2
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Reserved. Write only default values
D6–D4
R/W
000
DAC Auto Mute Control
000: Auto Mute disabled
001: DAC is auto muted if input data is DC for more than 100 consecutive inputs
010: DAC is auto muted if input data is DC for more than 200 consecutive inputs
011: DAC is auto muted if input data is DC for more than 400 consecutive inputs
100: DAC is auto muted if input data is DC for more than 800 consecutive inputs
101: DAC is auto muted if input data is DC for more than 1600 consecutive inputs
110: DAC is auto muted if input data is DC for more than 3200 consecutive inputs
111: DAC is auto muted if input data is DC for more than 6400 consecutive inputs
D3
R/W
1
Left DAC Channel Mute Control
0: Left DAC Channel not muted
1: Left DAC Channel muted
D2
R/W
1
Right DAC Channel Mute Control
0: Right DAC Channel not muted
1: Right DAC Channel muted
D1–D0
R/W
00
DAC Master Volume Control
00: Left and Right Channel have independent volume control
01: Left Channel Volume is controlled by Right Channel Volume Control setting
10: Right Channel Volume is controlled by Left Channel Volume Control setting
11: Reserved. Do not use
104
REGISTER MAP
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC36
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