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參數(shù)資料
| 型號(hào)： | TLV320DAC23RHDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 32-BIT DAC, PQCC28 |
| 封裝： | GREEN, PLASTIC, QFN-28 |
| 文件頁數(shù)： | 8/39頁 |
| 文件大小： | 664K |
| 代理商： | TLV320DAC23RHDRG4 |
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31
3 How to Use the DAC23
3.1
Control Interfaces
The TLV320DAC23 has many programmable features. The control interface is used to program the registers of the
device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The
state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.
MODE
INTERFACE
0
2-wire
1
SPI
3.1.1
SPI
In SPI mode, SDI carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320DAC23. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising
edge on CS after the sixteenth rising clock edge latches the data word into the DAC (see Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9]
Control address bits
B[8:0]
Control data bits
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
CS
SCLK
SDI
Figure 31. SPI Timing
3.1.2
2-Wire
In 2-wire mode, the data transfer uses SDI for the serial data and SCLK for the serial clock. The start condition is a
falling edge on SDIN while SCLK is high. The seven bits following the start condition determine the device on the
2-wire bus that receives the data. R/W determines the direction of the data transfer. The TLV320DAC23 is a write
only device and responds only if R/W is 0. The device operates only as a slave device whose address is selected
by setting the state of the CS pin as follows.
CS STATE
(Default = 0)
ADDRESS
0
0011010
1
0011011
The device that recognizes the address responds by pulling SDI low during the ninth clock cycle, acknowledging the
data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising
edge on SDI when SCLK is high (see Figure 3-2).
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