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參數資料
| 型號： | TLV5580IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | GREEN, PLASTIC, TSSOP-28 |
| 文件頁數： | 13/36頁 |
| 文件大小： | 478K |
| 代理商： | TLV5580IPWRG4 |
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TLV5580
8BIT, 80 MSPS LOW POWER A/D CONVERTER
SLAS205B DECEMBER 1998 REVISED OCTOBER 2003
www.ti.com
20
TLV5580 EVALUATION MODULE
TLV5580 EVM SETTINGS
CLOCK INPUT SETTINGS
REFERENCE
DESIGNATOR
FUNCTION
W1
Clock selection switch
12 J11: clock from pin1 on J11 connector
23 J9: clock from J9 SMA connector
W2
Clock source switch
J XTL: clock from onboard crystal oscillator
j CLK: clock from pin 1 on J11 connector (if W1/12) or J9 SMA connector (if W1/23)
NOTE: If set to XTL and a XTL oscillator is populated, no clock signal should be applied to J9 or J11, depending on the W1
setting.
W3
Clock output switch
12 Rising: clock output on J11 connector is the same phase as the clock to the digital output buffer. Data changes on rising
CLK edge.
23 Falling: clock output on J11 connector is the opposite phase as the digital output buffer. Data changes on falling CLK edge.
REFERENCE SETTINGS
REFERENCE
DESIGNATOR
FUNCTION
SW1
REFT external/internal switch
Jj REFT internal: REFT from TLV5580 internal reference
jJ REFT external: REFT from onboard voltage reference circuit
SW2
REFB external/internal switch
Jj REFB internal: REFB from TLV5580 internal reference
jJ REFB external: REFB from onboard voltage reference circuit
CONTROL SETTINGS
REFERENCE
DESIGNATOR
FUNCTION
W4
TLV5580 and digital output buffer output enable control (1)
J 5580-574 OE-connected: Connects OEs of TLV5580 and digital output buffer (574 buffer). Use this when no board-external
OE is used. In addition, close W5 to have both OEs permanently enabled.
j 5580-574OE-disconnected: Disconnects OEs of TLV5580 and digital output buffer (574 buffer). The OE for the output buffer
needs to be pulled low from pin 5 on J11 connector to enable. The OE for TLV5580 is independently controlled from pin 7 on
J11 connector (W5 open) or is permanently enabled if W5 is closed.
W5
TLV5580 and digital output buffer output enable control (2)
J 5580 OE to GND: Connects OEs of TLV5580 to GND. Additionally connects OE of 74ALS574 to GND if W4 is 5580-574
OE-connected.
j 5580 OE external: Enables control of OE of TLV5580 via pin 7 on J11 connector. When taken high (internal pulldown) the
output can be disabled.
W6
TLV5580 STDBY control
J Stdby: STDBY is active (high).
j Active: STDBY is low, via internal pulldown. STDBY can be taken high from pin 9 on J11 connector to enable standby mode.
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