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參數(shù)資料
型號(hào)： TLV5604IPWRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： DAC
英文描述： SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝： GREEN, PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 23/31頁(yè)
文件大小： 572K
代理商： TLV5604IPWRG4
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
AGND
9
Analog ground
AVDD
16
Analog supply
CS
6
I
Chip select. This terminal is active low.
DGND
8
Digital ground
DIN
4
I
Serial data input
DVDD
1
Digital supply
FS
7
I
Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
to the TLV5604.
PD
2
I
Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
This terminal is active low.
LDAC
3
I
Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
the serial interface. The DAC outputs are only updated when LDAC is low.
REFINAB
15
I
Voltage reference input for DACs A and B.
REFINCD
10
I
Voltage reference input for DACs C and D.
SCLK
5
I
Serial Clock input
OUTA
14
O
DAC A output
OUTB
13
O
DAC B output
OUTC
12
O
DAC C output
OUTD
11
O
DAC D output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DVDD, AVDD to GND)
7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage difference, (AVDD to DVDD)
–2.8 V to 2.8 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range
–0.3 V to DVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range
–0.3 V to AVDD + 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5604C
0
°C to 70°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV5604I
–40
°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
– 65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
相關(guān)PDF資料
PDF描述
TLV5604IPWG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604CDRG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604CPWRG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
TLV5604IDR SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
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