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參數資料
型號: TLV5604IPWRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數: 6/31頁
文件大小: 572K
代理商: TLV5604IPWRG4
TLV5604
2.7-V TO 5.5-V 10-BIT 3-
S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176B – DECEMBER 1997 – REVISED JULY 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the
TLV5604 is selected by A1 and A0 within the input word.
A1
A0
DAC
0
A
0
1
B
1
0
C
1
D
TLV5604 interfaced to TMS320C203 DSP
Hardware interfacing
Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP. The serial port is
configured in burst mode, with FSX generated by the TMS320C203 to provide the Frame Sync (FS) input to
the TLV5604. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The
general-purpose input/output port bits IO0 and IO1 are used to generate the Chip Select ( CS) and DAC Latch
Update ( LDAC ) inputs to the TLV5604. The active low Power Down ( PD ) is pulled high all the time to ensure
the DACs are enabled.
DX
CLKX
FSX
I/O 0
I/O 1
TMS320C203
SDIN
SCLK
FS
CS
LDAC
REF
VDD
PD
VOUTA
VOUTB
VOUTC
VOUTD
VSS
TLV5604
REFINAB
REFINCD
Figure 17. TLV5604 Interfaced with TMS320C203
Software
The application example generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins,
and it is quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency. The related interrupt service routine pulses
LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS
pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the
tsu(C16-FS) timing requirement will occur. To avoid this, the program waits until the transmission of the previous
word has been completed.
相關PDF資料
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TLV5604IPWG4 SERIAL INPUT LOADING, 8.5 us SETTLING TIME, 10-BIT DAC, PDSO16
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