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參數(shù)資料
| 型號(hào)： | TLV5610IYER |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PBGA20 |
| 封裝： | WAFER CHIP SCALE, 20 PIN |
| 文件頁(yè)數(shù)： | 2/17頁(yè) |
| 文件大小： | 345K |
| 代理商： | TLV5610IYER |
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TLV5610IYE
TLV5608IYE
SLAS393 OCTOBER 2003
www.ti.com
10
APPLICATION INFORMATION
GENERAL FUNCTION
The TLV5610IYE and TLV5608IYE are 8-channel, 12-bit, single supply DACs, based on a resistor string
architecture. They consist of a serial interface, a speed and power-down control logic, a reference input buffer,
a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by external reference) for each channel is given by:
REF
CODE
0x1000
[V]
where REF is the reference voltage and CODE is the digital input value. The input range is 0x000 to 0xFFF
for the TLV5610IYE and, 0x000 to 0xFFC for the TLV5608IYE. A power on reset initially puts the internal latches
to a defined state (all bits zero).
SERIAL INTERFACE
A falling edge of FS starts shifting the data on DIN starting with the MSB to the internal register on the falling
edges of SCLK. After 16 bits have been transferred, the content of the shift register is moved to one of the DAC
holding registers depending on the address bits within the data word. A logic 0 on the LDAC pin is required to
transfer the content of the DAC holding register to the DAC latch and to update the DAC outputs. LDAC is an
asynchronous input. It can be held low if a simultaneous update of all eight channels is not needed.
For daisy-chaining, DOUT provides the data sampled on DIN with a delay of 16 clock cycles.
SCLK
FS
DIN
SCLK
FS
F15
X
E0
X
E1
E14
E15
D0
D1
D14
D15
X
DIN
F15
X
E1
E0
E14
E15
X
D0
D1
D14
D15
X
DSP Mode:
C Mode:
Difference between DSP mode (MODE = N.C. or 0) and
C (MODE = 1) mode:
D In C mode FS needs to be held low until all 16 data bits have been transferred. If FS is driven high before
the 16th falling clock edge the data transfer is cancelled. The DAC is updated after a rising edge on FS.
D In DSP mode FS only needs to stay low for 20 ns and can go high before the 16th falling clock edge.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TLV5610IYZ | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DIGITAL-TO-ANALOG CONVERTER in a Wafer Chip-Scale Packagea??Pb-Free/Green |
| TLV5610IYZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 12B Octal DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5610IYZT | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 2.7V to 5.5V 12B Octal DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| TLV5613 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| TLV5613CDW | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12bit CMOS DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類(lèi)型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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