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參數(shù)資料
| 型號(hào)： | TLV5621EDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 321K |
| 代理商： | TLV5621EDR |
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
VDD = 3 V to 3.6 V, Vref = 1.25 V, GND = 0 V, RL = 10 k, CL = 100 pF, × 1 gain output range
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output slew rate, rising (DACA)
0.8
V/
s
Output slew rate, falling (DACA)
0.5
V/
s
Output slew rate (DACB, DACC, DACD)
1
V/
s
Output settling time, rising (DACA)
To 1/2 LSB,
VDD = 3 V
20
s
Output settling time, falling (DACA)
To 1/2 LSB,
VDD = 3 V
75
s
Output settling time, rising (DACB, DACC,
DACD)
To 1/2 LSB,
VDD = 3 V
10
s
Output settling time, falling (DACB, DACC,
DACD)
To 1/2 LSB,
VDD = 3 V
75
s
Output settling time, HWACT or ACT
↑ to
output volts (DACA) (see Note 14)
To 1/2 LSB,
VDD = 3 V
40
120
s
Output settling time, HWACT or ACT
↑ to
output volts (DACB, DACC, DACD)
(see Note 14)
To 1/2 LSB,
VDD = 3 V
25
75
s
Large-signal bandwidth
Measured at – 3 dB point
100
kHz
Digital crosstalk
CLK = 1-MHz square wave measured at DACA–DACD
–50
dB
Reference feedthrough
A, B, C, D inputs, See Note 15
–60
dB
Channel-to-channel isolation
A, B, C, D inputs, See Note 16
–60
dB
Channel-to-channel isolation when in
shutdown
A, B, C, D inputs
–40
dB
Reference bandwidth (DACA)
See Note 17
20
kHz
Reference bandwidth (DACB, DACC, DACD)
See Note 17
100
kHz
This is specified by characterization but is not production tested.
NOTES: 14. The ACT bit is latched on EN
↓.
15. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz.
16. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
with Vref input = 1 V dc + 1 VPP at 10 kHz.
17. Reference bandwidth is the –3 dB bandwidth with an ideal input at Vref = 1.25 V dc + 2 VPP and with a digital input code of full-scale
(range set to
× 1 and VDD = 5 V).
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| TLV5621EDRG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Low-Power Quadruple 8-Bit RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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| TLV5621ID | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8bit DAC 4Chl RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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