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參數資料
| 型號： | TLV5621EDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數： | 6/19頁 |
| 文件大小： | 321K |
| 代理商： | TLV5621EDR |
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
POSITIVE RISE TIME AND SETTLING TIME
VDD = 3 V
TA = 25°C
Code 00 to
FF Hex
Range =
×2
Vref = 1.25 V
(see Notes
A and B)
t – Time –
s
02
4
6
8
10
12
–
Output
V
oltage
–
V
14
16
18
20
–1
– 0.5
0.5
1
1.5
2
2.5
0
3
V
O
NOTES: A. Rise time = 2.05
s, positive slew rate = 0.96 V/s,
settling time = 4.5
s.
B. For DACB, DACC, and DACD
Figure 10
NEGATIVE FALL TIME AND SETTLING TIME
VDD = 3 V
TA = 25°C
Code FF to
00 Hex
Range =
×2
Vref = 1.25 V
(see Notes
A and B)
t – Time –
s
02
4
6
8
10
12
–
Output
V
oltage
–
V
14
16
18
20
–1
– 0.5
0.5
1
1.5
2
2.5
0
3
V
O
NOTES: A. Fall time = 4.25
s, negative slew rate = 0.46 V/s,
settling time = 8.5
s.
B. For DACB, DACC, and DACD
Figure 11
2
1.8
1.4
1.2
1
2.8
1.6
0
10
2030
405060
–
DAC
Output
V
oltage
–
V
2.4
2.2
2.6
DAC OUTPUT VOLTAGE
vs
LOAD RESISTANCE
3
70
80
90
100
V
O
RL – Load Resistance – k
VDD = 3 V
Vref = 1.5 V
Range =
×2
(see Note A)
NOTE A: For DACB, DACC, and DACD
Figure 12
0.8
0.6
0.2
0
010
20
30
40
50
60
1
1.4
1.6
70
80
90
100
0.4
1.2
DAC OUTPUT VOLTAGE
vs
LOAD RESISTANCE
VDD = 3 V
Vref = 1.5 V
Range =
×1
(see Note A)
–
DAC
Output
V
oltage
–
V
O
RL – Load Resistance – k
NOTE A: For DACB, DACC, and DACD
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