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參數(shù)資料
| 型號(hào)： | TLV5621IDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大小： | 321K |
| 代理商： | TLV5621IDR |
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
control register
The control register contains ten active bits. Four bits are range select bits as on the TLC5620. The register also
contains a software shutdown bit (ACT) and four shutdown inhibit bits (SIA, SIB, SIC, SID). The shutdown inhibit
bits act on each DAC (DACA through DACD). The mode select bit is used to change between single and double
buffered modes. The bits in the control register are listed in Table 2.
Table 2. Control Register Bits
BIT
FUNCTION
MODE
Selection bit for type of interface (see data interface section)
RNG A
Range select bit for DACA, 0 =
1, 1 = 2
RNG B
Range select bit for DACB, 0 =
1, 1 = 2
RNG C
Range select bit for DACC, 0 =
1, 1 = 2
RNG D
Range select bit for DACD, 0 =
1, 1 = 2
SIA
Shutdown inhibit bit for DACA
SIB
Shutdown inhibit bit for DACB
SIC
Shutdown inhibit bit for DACC
SID
Shutdown inhibit bit for DACD
ACT
Software shutdown bit
The SIx bits inhibit the actions of the shutdown bits as shown in Table 3. When the ACT bit is 1 or the HWACT
signal is high (active), the inhibit bits act as enable bits in inverse logic terms. The ACT software shutdown bit
and HWACT (asynchronously acting hardware terminal) are logically ORed together.
This configuration allows any combination of DACs to be shut down to save power.
Table 3. Shutdown Inhibit Bits and HWACT Signal
SIx
ACT
HWACT
DACx STATUS
0
L
Shutdown (see Note 1)
0
H
Shutdown
0
1
L
Shutdown
0
1
H
Active (see Note 1)
1
0
L
Active
1
0
H
Active
1
L
Active
1
H
Active
NOTE 1: Sense of HWACT terminal and ACT bit were changed from early
versions of this specification.
The values of the input address select bits, A0 and A1, and the updated DAC are listed in Table 4.
Table 4. Serial Input Decode
INPUT ADDRESS SELECT BITS
DAC UPDATED
A1
A0
DAC UPDATED
0
DACA
0
1
DACB
1
0
DACC
1
DACD
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