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參數資料
| 型號： | TLV5625IDR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數： | 11/15頁 |
| 文件大小： | 212K |
| 代理商： | TLV5625IDR |
TLV5625
2.7V TO 5.5V LOW POWER DUAL 8BIT DIGITALTOANALOG
CONVERTER WITH POWER DOWN
SLAS233D JULY 1999 REVISED JULY 2002
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIH
High-level digital input current
VI = VDD
1
A
IIL
Low-level digital input current
VI = 0 V
1
A
Ci
Input capacitance
8
pF
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ts(FS)
Output settling time, full scale
RL = 10 k,CL = 100 pF,
Fast
1
3
s
ts(FS)
Output settling time, full scale
RL = 10 k,CL = 100 pF,
See Note 11
Slow
3
10
s
ts(CC)
Output settling time, code to code
RL = 10 k,CL = 100 pF,
Fast
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,CL = 100 pF,
See Note 12
Slow
2
s
SR
Slew rate
RL = 10 k,CL = 100 pF,
Fast
3
V/ s
SR
Slew rate
RL = 10 k,CL = 100 pF,
See Note 13
Slow
0.5
V/
s
Glitch energy
DIN = 0 to 1,
FCLK = 100 kHz,
CS = VDD
5
nVs
SNR
Signal-to-noise ratio
52
54
SINAD
Signal-to-noise + distortion
fs = 102 kSPS, fout = 1 kHz,
48
49
dB
THD
Total harmonic distortion
fs = 102 kSPS, fout = 1 kHz,
RL = 10 k,CL = 100 pF
50
48
dB
SFDR
Spurious free dynamic range
RL = 10 k ,CL = 100 pF
48
50
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
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