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參數資料
| 型號： | TLV5637IDG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 2.8 us SETTLING TIME, 10-BIT DAC, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數： | 4/21頁 |
| 文件大?。?/td> | 422K |
| 代理商： | TLV5637IDG4 |
www.ti.com
APPLICATION INFORMATION
REFERENCE BITS
EXAMPLES OF OPERATION:
SLAS224C – JUNE 1999 – REVISED JUNE 2007
REF1
REF0
REFERENCE
0
External
0
1
1.024V
1
0
2.048V
1
External
CAUTION:
If external refeence voltage is applied to the REF pin, external reference MUST
be selected.
1. Set DAC A output, select fast mode, select internal reference at 2.048V:
a.
Set reference voltage to 2.048V (CONTROL register)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
b.
Write new DAC A value and update DAC A output:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
New DAC A output value
0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the
CONTROL register again.
2. Set DAC B output, select fast mode, select external reference:
a.
Select external reference (CONTROL register):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
b.
Write new DAC B value to BUFFER and update DAC B output:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
New BUFFER content and DAC B output value
0
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the
CONTROL register again.
1. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal
reference at 1.024V:
a.
Set reference voltage to 1.024V (CONTROL register):
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
b.
Write data for DAC B to BUFFER:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
New DAC B value
0
c.
Write new DAC A value and update DAC A and B simultaneously:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
New DAC A value
0
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
2. Set power down mode:
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
1
X
X = Don't care
12
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