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參數資料
| 型號： | TLV990APFB |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數： | 3/24頁 |
| 文件大小： | 328K |
| 代理商： | TLV990APFB |
TLV990A
3-V, 10-BIT, 28-MSPS AREA CCD AND VIDEO SIGNAL PROCESSOR
SLAS297 – SEPTEMBER 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
REGISTER DEFINITION
serial input data format
DI15
DI14
DI13
DI12
DI11
DI10
DI9
DI8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
X
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
D9–D0
0
Control register1
10-bit data be to written into the selected register
0
1
PGA gain register
0
1
0
User DAC1 register
0
1
User DAC2 register
0
1
0
Coarse offset DAC
0
1
0
1
Fine offset DAC
0
1
0
Digital Vb register (sets reference code level at the ADC output during the optical black interval)
0
1
Optical black setup register (sets the number of black pixels per line for digital averaging)
1
0
Hot/cold pixel limit register (sets the limit for maximum positive deviation of optical black pixel from Vb value)
1
0
1
Reserved
1
0
1
0
Control register2 (sets the weight for digital filtering and video modes)
1
0
1
Blanking data register (The data in this register appears at digital output during blanking (BLKG is low))
1
0
ADCCLK internal programmable delay register
1
0
1
SR and SV internal programmable delay register
1
0
Test register
control register1 format
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
STBY
PDD1
PDD2
ACD
AFD
OBM
X
SRSV
RTOB
RTSY
control register1 description
BIT
NAME
DESCRIPTION
D9
STBY
Device power-down control: 1 = standby, 0 = active (default)
D8
PDD1
Power-down user DAC1: 1 = standby, 0 = active (default)
D7
PDD2
Power-down user DAC2: 1 = standby, 0 = active (default)
D6
ACD
Coarse-offset DAC mode control:
0 = autocalibration (default), 1 = bypass autocalibration.
Note: When D6 is set to 0, D5 must also be set to 0 (automode). Otherwise, the automode will be disabled on both offset DACs.
D5
AFD
Fine offset DAC mode control:
0 = autocalibration (default), 1 = bypass autocalibration.
Note: D5 can be set to 0 with or without D6 being set to 0.
D4
OBM
This bit initiates the offset DACs starting sequence.
0 = coarse-offset DAC starts first (default)
1 = fine-offset DAC starts first
D3
X
Reserved
D2
SRSV
This bit specifies the polarity of SR and SV input pulses.
0 – SR/SV active low (default)
1 – SR/SV active high
D1
RTOB
Writing 1 to this bit will reset calculated black-level results in the digital averager.
D0
RTSY
Writing 1 to this bit will reset entire system to the default settings (edge sensitive).
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