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參數資料
| 型號： | TMDS261BPAGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數： | 49/49頁 |
| 文件大小： | 11321K |
| 代理商： | TMDS261BPAGR |
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DISSIPATION RATINGS
THERMAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
www.ti.com .......................................................................................................................................................................................... SLLS987 – SEPTEMBER 2009
DERATING FACTOR(1)
TA = 70°C
PACKAGE
PCB JEDEC STANDARD
TA ≤ 25°C
ABOVE TA = 25°C
POWER RATING
Low-K
1066 mW
10.66 mW/°C
586 mW
64-pin TQFP (PAG)
High-K
1481 mW
14.8 mW/°C
814 mW
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX(1)
UNIT
RθJB
Junction-to-board thermal resistance
37.13
°C/W
RθJC
Junction-to-case thermal resistance
15.3
°C/W
Device power dissipation in normal
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
PD(1)
mode
TMDS data pattern; HPD_SINK = HIGH, S1/S2 =
560
780
mW
LOW/HIGH, HIGH/HIGH
Device power dissipation in standby
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
PD(2)
mode
TMDS data pattern; HPD_SINK = HIGH, S1 = HIGH,
10
20
mW
S2 = LOW
Device power dissipation in low-power
PSD
LP = LOW
1
2
mW
mode
Device power dissipation in normal
LP = HIGH, no TMDS input clock, HPD_SINK =
PNCLK
40
65
mW
mode with no active TMDS input clock
HIGH, S1/S2 = LOW/HIGH, HIGH/HIGH
(1)
The maximum rating is simulated under 3.6-V VCC across worst-case temperature and process variation. Typical conditions are
simulated at 3.3-V VCC, 25°C with nominal process material.
MIN
NOM
MAX
UNIT
VCC
Supply voltage
3
3.3
3.6
V
TA
Operating free-air temperature
0
70
°C
TMDS DIFFERENTIAL OUTPUT AND INPUT PINS
VID(pp)
Peak-to-peak input differential voltage
0.15
1.56
V
VIC
Input common-mode voltage
VCC – 0.4
VCC + 0.01
V
tIN_Rise_Fall
TMDS input rise and fall time
75
ps
VIN_PRE
Acceptable pre-emphasis on TMDS input signals. Note that an input signal
See (Figure 26)
into TMDS261B with longer pre-emphasis duration and/or larger
pre-emphasis ampltidue, could result in over-equalization.
AVCC
TMDS output termination voltage
3
3.3
3.6
V
dR
Data rate
3
Gbps
RVSadj
Resistor for TMDS-compliant voltage output swing
3.66
4.02
4.47
k
RT
Termination resistance
45
50
55
DDC PINS
VI
Input voltage
0
5.5
V
dR(I2C)
I2C data rate
100
Kbps
HPD AND CONTROL PINS
VIH
High-level input voltage
2
5.5
V
VIL
Low-level input voltage
0
0.8
V
Copyright 2009, Texas Instruments Incorporated
9
Product Folder Link(s) :TMDS261B
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