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參數(shù)資料
型號： TMJ320C6211GDP167
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 47/83頁
文件大小： 1176K
代理商： TMJ320C6211GDP167
TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles
§
(see Figure 18
Figure 19)
NO.
C6211
150
C6211
167
C6211B
150
C6211B
167
C6211BGFNA
150
UNIT
MIN
MAX
MIN
MAX
3
4
6
7
t
su(EDV-AREH)
t
h(AREH-EDV)
t
su(ARDY-EKOH)
t
h(EKOH-ARDY)
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
Setup time, ARDY valid before ECLKOUT
high
Hold time, ARDY valid after ECLKOUT
high
9
1
3
1
9
2
3
2
ns
ns
ns
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for asynchronous memory
cycles for C6211 and C6211B
§
(see Figure 18
Figure 19)
NO.
PARAMETER
C6211
150
C6211
167
C6211B
150
C6211B
167
UNIT
MIN
MAX
MIN
MAX
1
2
5
8
9
10
t
osu(SELV-AREL)
t
oh(AREH-SELIV)
t
d(EKOH-AREV)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
d(EKOH-AWEV)
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUT high to ARE vaild
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUT high to AWE vaild
RS * E
3
RH * E
3
RS * E
3
RH * E
3
ns
ns
ns
ns
ns
ns
1.5
8
1.5
8
WS * E
3
WH * E
3
WS * E
3
WH * E
3
1.5
8
1.2
8
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
E = ECLKOUT period in ns
Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].
switching characteristics over recommended operating conditions for asynchronous memory
cycles for C6211BGFNA
§
(see Figure 18
Figure 19)
NO.
PARAMETER
C6211BGFNA
150
MIN
RS * E
3
RH * E
3
1.5
WS * E
3
WH * E
3
UNIT
MAX
1
2
5
8
9
10
t
osu(SELV-AREL)
t
oh(AREH-SELIV)
t
d(EKOH-AREV)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
d(EKOH-AWEV)
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUT high to ARE vaild
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUT high to AWE vaild
ns
ns
ns
ns
ns
ns
8
1
8
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
E = ECLKOUT period in ns
Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].
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