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參數資料
| 型號： | TMJ320C6211GLZ167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 64/83頁 |
| 文件大?。?/td> | 1176K |
| 代理商： | TMJ320C6211GLZ167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
64
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
HOST-PORT INTERFACE TIMING (CONTINUED)
timing requirements for host-port interface cycles [C6211BGFNA/C6211B]
(see Figure 33,
Figure 34, Figure 35, and Figure 36)
NO.
C6211B
150
C6211B
167
C6211BGFNA
150
UNIT
MIN
5
4
4P
4P
5
3
5
3
MAX
1
2
3
4
10
11
12
13
t
su(SELV-HSTBL)
t
h(HSTBL-SELV)
t
w(HSTBL)
t
w(HSTBH)
t
su(SELV-HASL)
t
h(HASL-SELV)
t
su(HDV-HSTBH)
t
h(HSTBH-HDV)
Setup time, select signals
§
valid before HSTROBE low
Hold time, select signals
§
valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals
§
valid before HAS low
Hold time, select signals
§
valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
ns
ns
ns
ns
ns
ns
ns
ns
14
t
h(HRDYL-HSTBL)
2
ns
18
19
t
su(HASL-HSTBL)
t
h(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
2
ns
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§
Select signals include: HCNTL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface
cycles [C6211BGFNA/C6211B]
(see Figure 33, Figure 34, Figure 35, and Figure 36)
NO.
PARAMETER
C6211BGFNA
150
C6211B
150
C6211B
167
UNIT
MIN
MAX
13
13
MIN
MAX
12
12
5
6
t
d(HCS-HRDY)
t
d(HSTBL-HRDYH)
Delay time, HCS to HRDY
Delay time, HSTROBE low to HRDY high
#
1
3
1
3
ns
ns
7
t
d(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for
an HPI read
2
2
ns
8
9
15
t
d(HDV-HRDYL)
t
oh(HSTBH-HDV)
t
d(HSTBH-HDHZ)
t
d(HSTBL-HDV)
t
d(HSTBH-HRDYH)
t
d(HASL-HRDYH)
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
2P
4
2P
13
13
2P
4
2P
12
12
ns
ns
ns
3
3
3
3
16
Delay time, HSTROBE low to HD valid
3
13
3
12
ns
17
20
Delay time, HSTROBE high to HRDY high
||
Delay time, HAS low to HRDY high
3
3
13
13
3
3
12
12
ns
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
||
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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