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參數(shù)資料
| 型號(hào)： | TMP320C6211PYP167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 61/83頁(yè) |
| 文件大小： | 1176K |
| 代理商： | TMP320C6211PYP167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
61
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
RESET TIMING (CONTINUED)
13
12
11
10
9
8
7
6
5
4
3
2
15
14
1
CLKOUT1
CLKOUT2
RESET
ECLKIN
EMIF Z Group
EMIF High Group
EMIF Low Group
High Group
Z Group
HD[8, 4:3]
§
§
ECLKIN should be provided during reset in order to drive EMIF signals to the correct reset values. ECLKOUT continues to clock as long as
ECLKIN is provided.
EMIF Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE
EMIF high group consists of: HOLDA
EMIF low group consists of:
BUSREQ
High group consists of:
HRDY and HINT
Z group consists of:
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
HD[8, 4:3] are the endianness and boot configuration pins during device reset.
Figure 31. Reset Timing
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