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參數資料
| 型號： | TMP320F2810PBKAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 66/103頁 |
| 文件大小： | 1341K |
| 代理商： | TMP320F2810PBKAEP |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
PWM characteristics
Characteristics of the PWMs are as follows:
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and
after
PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
–
PDPINTA pin status is reflected in bit 8 of COMCONA register.
–
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
–
–
–
–
–
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)
—
one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and
CAP4/5 can also be used as QEP inputs to the QEP circuit.]
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
–
–
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
external ADC start-of-conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (ESOCA/B) for external ADC interface.
EVASOC and EVBSOC are muxed with T2CTRIP and T4CTRIP, respectively.
P
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| TMP320F2810PBKS | 功能描述:IC DSP W/FLASH128=LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:TMS320F281x, C2000™ 產品培訓模塊:XLP Deep Sleep Mode 8-bit PIC® Microcontroller Portfolio 標準包裝:22 系列:PIC® XLP™ 18F 核心處理器:PIC 芯體尺寸:8-位 速度:48MHz 連通性:I²C，SPI，UART/USART，USB 外圍設備:欠壓檢測/復位，POR，PWM，WDT 輸入/輸出數:14 程序存儲器容量:8KB（4K x 16） 程序存儲器類型:閃存 EEPROM 大小:256 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 5.5 V 數據轉換器:A/D 11x10b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:20-DIP（0.300"，7.62mm） 包裝:管件 產品目錄頁面:642 (CN2011-ZH PDF) 配用:DV164126-ND - KIT DEVELOPMENT USB W/PICKIT 2DM164127-ND - KIT DEVELOPMENT USB 18F14/13K50AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP |
| TMP320F2810PGFA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMP320F2810PGFAEP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Digital Signal Processors |
| TMP320F2810PGFS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSORS |
| TMP320F2811GHHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TMS320R2811, TMS320R2812 Digital Signal Processors |
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