
SBOS441C
– SEPTEMBER 2009 – REVISED FEBRUARY 2011
Bus Overview
Read/Write Operations
The TMP431/32 are SMBus interface-compatible. In
Accessing a particular register on the TMP431/32 is
SMBus protocol, the device that initiates the transfer
accomplished by writing the appropriate value to the
is called a master, and the devices controlled by the
Pointer Register. The value for the Pointer Register is
master are slaves. The bus must be controlled by a
the first byte transferred after the slave address byte
master device that generates the serial clock (SCL),
with the R/W bit low. Every write operation to the
controls the bus access, and generates the START
TMP431/32 require a value for the Pointer Register
and STOP conditions.
To address a specific device, a START condition is
When reading from the TMP431/32, the last value
initiated. START is indicated by pulling the data line
stored in the Pointer Register by a write operation is
(SDA) from a high to low logic level while SCL is
used to determine which register is read by a read
high. All slaves on the bus shift in the slave address
operation. To change the register pointer for a read
byte, with the last bit indicating whether a read or
operation, a new value must be written to the Pointer
write operation is intended. During the ninth clock
Register. This transaction is accomplished by issuing
pulse, the slave being addressed responds to the
a slave address byte with the R/W bit low, followed
master by generating an Acknowledge and pulling
by the Pointer Register byte. No additional data are
SDA low.
required. The master can then generate a START
condition and send the slave address byte with the
Data transfer is then initiated and sent over eight
R/W bit high to initiate the read command. See
clock pulses followed by an Acknowledge bit. During
Figure 18 for details of this sequence. If repeated
data transfer SDA must remain stable while SCL is
reads from the same register are desired, it is not
high, because any change in SDA while SCL is high
necessary to continually send the Pointer Register
is interpreted as a control signal.
bytes, because the TMP431/32 retain the Pointer
Register value until it is changed by the next write
Once all data have been transferred, the master
operation. Note that register bytes are sent MSB first,
generates a STOP condition. STOP is indicated by
followed by the LSB.
pulling SDA from low to high, while SCL is high.
TIMING DIAGRAMS
Serial Interface
The
TMP431/32
are
Two-Wire
and
The TMP431/32 operate only as slave devices on
either the Two-Wire bus or the SMBus. Connections
the various operations on the TMP431/32. Bus
to either bus are made via the open-drain I/O lines,
definitions are given below. Parameters for
Figure 16SDA and SCL. The SDA and SCL pins feature
integrated spike suppression filters and Schmitt
triggers to minimize the effects of input spikes and
Bus Idle: Both SDA and SCL lines remain high.
bus noise. The TMP431/32 support the transmission
protocol for fast (1kHz to 400kHz) and high-speed
Start Data Transfer: A change in the state of the
(1kHz
to
3.4MHz)
modes.
All
data
bytes
are
SDA line, from high to low, while the SCL line is high,
transmitted MSB first.
defines a START condition. Each data transfer is
initiated with a START condition.
Serial Bus Address
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
To communicate with the TMP431/32, the master
defines
a
STOP
condition.
Each
data
transfer
must first address slave devices via a slave address
terminates with a STOP or a repeated START
byte. The slave address byte consists of seven
condition.
address bits, and a direction bit that indicates the
intent of executing a read or write operation.
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
The address of the TMP431A/32A/31C is 4Ch
limited and is determined by the master device. The
(1001100b). The address of the TMP431B/32B/31D
receiver acknowledges the transfer of data.
is 4Dh (1001101b).
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