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參數(shù)資料
型號(hào): TMP431BDGKT
廠商: TEXAS INSTRUMENTS INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO8
封裝: GREEN, PLASTIC, MSOP-8
文件頁數(shù): 19/40頁
文件大小: 790K
代理商: TMP431BDGKT
SCL
SDA
t
(LOW)
t
R
t
F
t
(HDSTA)
t
(HDSTA)
t
(HDDAT)
t
(BUF)
t
(SUDAT)
t
(HIGH)
t
(SUSTA)
t
(SUSTO)
P
S
P
SBOS441C
– SEPTEMBER 2009 – REVISED FEBRUARY 2011
Acknowledge:
Each
receiving
device,
when
period of the Acknowledge clock pulse. Setup and
addressed, is obliged to generate an Acknowledge
hold times must be taken into account. On a master
bit. A device that acknowledges must pull down the
receive, data transfer termination can be signaled by
SDA line during the Acknowledge clock pulse in such
the master generating a Not-Acknowledge on the last
a way that the SDA line is stable low during the high
byte that has been transmitted by the slave.
Figure 16. Two-Wire Timing Diagram
Table 16. Timing Diagram Definitions for Figure 16
FAST MODE
HIGH-SPEED MODE
PARAMETER
MIN
MAX
MIN
MAX
UNITS
SCL Operating Frequency
f(SCL)
0.001
0.4
0.001
3.4
MHZ
Bus Free Time Between STOP
ns
t(BUF)
600
160
and START Condition
Hold time after repeated START
condition. After this period, the
t(HDSTA)
100
ns
first clock is generated.
Repeated START Condition Setup
t(SUSTA)
100
ns
Time
STOP Condition Setup Time
t(SUSTO)
100
ns
Data Hold Time
t(HDDAT)
0(1)
0(2)
ns
Data Setup Time
t(SUDAT)
100
10
ns
SCL Clock LOW Period
t(LOW)
1300
160
ns
SCL Clock HIGH Period
t(HIGH)
600
60
ns
Clock/Data Fall Time
tF
300
160
ns
Clock/Data Rise Time
300
160
ns
tR
for SCLK
≤ 100kHz
1000
ns
(1)
For cases with fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater
than 20ns.
(2)
For cases with fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
26
2009–2011, Texas Instruments Incorporated
Product Folder Link(s): TMP431 TMP432
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