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參數資料
型號： TMX320C6413GTS500
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點數字信號處理器
文件頁數： 36/140頁
文件大小： 1958K
代理商： TMX320C6413GTS500
EDMA Channel Synchronization Events
36
April 2004
Revised May 2005
SPRS247E
2.7
EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 2
21 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the C6413/C6410 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the EDMA
event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,
EERH). The priority of each event can be specified independently in the transfer parameters stored in the
EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are
enabled, captured, processed, linked, chained, and cleared, etc., see the
TMS320C6000 DSP Enhanced
Direct Memory Access (EDMA) Controller Reference Guide
(literature number SPRU234).
Table 2
21. TMS320C6413/C6410 EDMA Channel Synchronization Events
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DSP_INT
TINT0
TINT1
SD_INTA
HPI-to-DSP interrupt
Timer 0 interrupt
Timer 1 interrupt
EMIFA SDRAM timer interrupt
GP0 event 4/External interrupt pin 4
GP0 event 5/External interrupt pin 5
GP0 event 6/External interrupt pin 6
GP0 event 7/External interrupt pin 7
GP0 event 0
GP0 event 1
GP0 event 2
GP0 event 3
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
None
Timer 2 interrupt
None
None
None
None
McASP0 transmit even event
McASP0 transmit odd event
McASP0 transmit event
McASP0 receive even event
McASP0 receive odd event
McASP0 receive event
McASP1 transmit even event
McASP1 transmit odd event
McASP1 transmit event
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
GPINT0
GPINT1
GPINT2
GPINT3
XEVT0
REVT0
XEVT1
REVT1
–
TINT2
–
–
–
–
AXEVTE0
AXEVTO0
AXEVT0
AREVTE0
AREVTO0
AREVT0
AXEVTE1
AXEVTO1
AXEVT1
16
18
19
20
27
28
29
30
31
32
33
34
35
36
37
38
39
40
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the
TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide
(literature number SPRU234).
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相關代理商/技術參數
參數描述
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TMX320C6413GTSA500 制造商:TI 制造商全稱:Texas Instruments 功能描述:Fixed-Point Digital Signal Processors
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