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參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 52/134頁
文件大小： 600K
代理商： TP6508
P.49
Extended Indexed Register SREG 07 : CPU Start address Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-3 CPU start address bit 0 to 3
D4-7 Reserved
Bit 0-3
These bit are used to set the CPU start address that specifies the offset from original
address point to the first byte of BANK 0. It can solve the Bank(Window) boundary
problem. The unit size of CPU start address is in 4 KB, so we can adjust the offset
address domain from 0 to 60 KB.
Reserved.
Bit 4-7
Extended Indexed Register SREG 08 : Extended Memory Bank C Select Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-4 Memory bank C select bit 0 to 4
D5-7 Reserved
Bit 0-4
When the TP6508 is configured with over 512k-byte display memory, a segment memory i.e. , 64K-
byte, only access a small part of the display region. These bits help the user to access the remaining
pixel data. When the user wants to move lots of pixel data from one bank to another, the microproces-
sor suffers from executing I/O write to modify the content of the bank select register. With its dual
and overlapping windowsarchitecture, operations performance has improved drastically.Each window
is associated with a four-bit bank select register. When the user wants to translate a good deal of
pixel data from one bank to another, he can programs two bank registers before translation once
instead of the modifying every pixel data movement. These bits are associated with the window down
address region from Hex A0000 to Hex AFFFF.
Reserved.
Bit 5-7
Extended Indexed Register SREG 09 : Extended Memory Bank D Select Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-4 Memory bank D select bit 0 to 4
D5-7 Reserved
Bit 0-4
These bits perform the same function as with the previous register except that they
are associated with the window down address region from Hex B0000 to Hex BFFFF
under SREG 06 bit-1 being set to logical 0. When SREG 06 bit-1 is set to logical 1,
they are associated with the same address region from Hex A0000 to Hex AFFFF.
Reserved.
Bit 5-7
Extended Indexed Register SREG E0,E1,E2 : Scratched Register 1,2,3
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-7 Reserved
相關PDF資料
PDF描述
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