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參數資料
| 型號： | TPA2011D1YFFT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3.24 W, 1 CHANNEL, AUDIO AMPLIFIER, BGA9 |
| 封裝： | 1.21 X 1.16 MM, 0.40 MM PITCH, GREEN, PLASTIC, DSBGA-9 |
| 文件頁數： | 10/24頁 |
| 文件大小： | 670K |
| 代理商： | TPA2011D1YFFT |
SLOS626A – DECEMBER 2009 – REVISED MAY 2010
www.ti.com
PRINTED CIRCUIT BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 35 shows the appropriate diameters for a WCSP layout.
Figure 35. Land Pattern Image and Dimensions
SOLDER PAD
SOLDER MASK
COPPER
STENCIL
COPPER PAD
STENCIL OPENING(6)(7)
DEFINITIONS
OPENING(5)
THICKNESS
Nonsolder mask
1 oz max
0.275 mm x 0.275 mm Sq.
0.23 mm
0.310 mm
0.1 mm thick
defined (NSMD)
(0.032 mm)
(rounded corners)
1. Circuit traces from NSMD defined PWB lands should be 75 mm to 100 mm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Best reliability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
3. Recommend solder paste is Type 3 or Type 4.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 mm on top of the copper circuit pattern
6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils give inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
Figure 36. Layout Snapshot
An on-pad via is not required to route the middle ball B2 (PVDD) of the TPA2011D1. Just short ball B2 (PVDD) to
ball B1 (VDD) and connect both to the supply trace as shown in Figure 36. This simplifies board routing and
saves manufacturing cost.
18
Copyright 2009–2010, Texas Instruments Incorporated
Product Folder Link(s) :TPA2011D1
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