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參數資料
型號: TPA2016D2RTJT
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 2.8 W, 2 CHANNEL, AUDIO AMPLIFIER, PQCC20
封裝: 4 X 4 MM, GREEN, PLASTIC, QFN-20
文件頁數: 13/38頁
文件大小: 1216K
代理商: TPA2016D2RTJT
Register(N)
8-BitDatafor
Register(N+1)
SINGLE-AND MULTIPLE-BYTE TRANSFERS
SINGLE-BYTE WRITE
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0 ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Start
Condition
Stop
Condition
Acknowledge
I2CDeviceAddressand
Read/WriteBit
Register
DataByte
SLOS524D – JUNE 2008 – REVISED AUGUST 2009........................................................................................................................................................ www.ti.com
address and the read/write (R/W) bit to open communication with another device, and then waits for an
acknowledge condition. The TPA2016D2 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this acknowledgment occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 5 V, use pull-up resistors between 1 k
and 2 k.
Figure 36. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 36.
The serial control interface supports both single-byte and multi-byte read/write operations for all registers.
During multiple-byte read operations, the TPA2016D2 responds with data, one byte at a time, starting at the
register assigned, as long as the master device continues to respond with acknowledgments.
The TPA2016D2 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of
data subsequently transmitted, before a stop or start is transmitted, determines the number of registers written.
As Figure 37 shows, a single-byte data write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data
transfer. For a write data transfer, the read/write bit must be set to '0'. After receiving the correct I2C device
address and the read/write bit, the TPA2016D2 responds with an acknowledge bit. Next, the master transmits the
register byte corresponding to the TPA2016D2 internal memory address being accessed. After receiving the
register byte, the TPA2016D2 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the register byte, the TPA2016D2
again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Figure 37. Single-Byte Write Transfer
20
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2016D2
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相關代理商/技術參數
參數描述
TPA2016D2V1YZHR 制造商:Texas Instruments 功能描述:
TPA2016D2YZHR 功能描述:音頻放大器 1.7W/Ch Stereo Class D Aud Amp RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
TPA2016D2YZHT 功能描述:音頻放大器 1.7W/Ch Stereo Class D Aud Amp RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
TPA2016DYZHT2 制造商:Texas Instruments 功能描述:
TPA2017D2 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.8-W/Ch Stereo Class-D Audio Amplifier with SmartGainTM Dynamic Range Compression and AGC
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