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參數(shù)資料
| 型號(hào)： | TPA2050D4YZKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25 |
| 封裝： | 2.61 X 2.61 MM, GREEN, DSBGA-25 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大小： | 931K |
| 代理商： | TPA2050D4YZKR |
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DETAILED DESCRIPTION
GENERAL I
2C OPERATION
SINGLE AND MULTI-BYTE TRANSFERS
SLOS544 – JULY 2008....................................................................................................................................................................................................... www.ti.com
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transistions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transistion on
SDA indicates a start and a low-to-high transistion indicates a stop. Normal data-bit transistions bust occur within
the low time of the clock period. Figure 43 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an
acknowledge condition. The TPA2050D4 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 5 V, use pull-up resistors between 1 k
and 2 k.
Figure 43. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. Figure 43 shows a generic data
transfer sequence.
The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During
multi-byte reads, the TPA2050D4 responds with data, one byte at a time, starting at the register assigned
provided the master devices continues to respond with acknowledgements.
The TPA2050D4 supports sequential I2C addressing. For write transactions, if a register is issued followed by
data for that register and all the remaining registers that follow, a sequential I2C write transaction has occurred.
For I2C sequential write transactions, the register issued then serves as the starting point and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many registers are written to.
14
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPA2050D4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPA2050D4YZKR | 制造商:Texas Instruments 功能描述:Audio Power Amplifier IC |
| TPA2050D4YZKT | 功能描述:音頻放大器 1.4 W/CH Stereo Class-D Audio Subsys RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TPA2051D3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.9 W/Channel Mono Class-D Audio Subsystem with DirectPath? Headphone Amplifier & SpeakerGuard? |
| TPA2051D3AYFFR | 制造商:TI 功能描述:Audio Subsystem |
| TPA2051D3YFFEVM | 功能描述:音頻 IC 開發(fā)工具 TPA2051D3YFF Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
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