
COMPONENT LOCATION
Trace Width
EFFICIENCY AND THERMAL INFORMATION
JA
1
θ
=
= 148 C/W
Derating Factor
0.0068
°
(3)
o
A
J
JA Dmax
T MAX
θ P
150
148(0.2)
120 C
=
-
=
-
=
(4)
OPERATION WITH DACS AND CODECS
www.ti.com ..................................................................................................................................................... SLOS641A – JUNE 2009 – REVISED OCTOBER 2009
Table 8. Land Pattern Dimensions(1)(2)(3)(4)
SOLDER PAD
SOLDER MASK(5)
COPPER
STENCIL(6) (7)
STENCIL
COPPER PAD
DEFINITIONS
OPENING
THICKNESS
OPENING
THICKNESS
Nonsolder mask
230
m
310
m
275
m x 275 m Sq.
1 oz max (32
m)
100
m thick
defined (NSMD)
(+0.0, –25
m)
(+0.0, –25
m)
(rounded corners)
(1)
Circuit traces from NSMD defined PWB lands should be 75
m to 100 m wide in the exposed area inside the solder mask opening.
Wider trace widths reduce device stand off and impact reliability.
(2)
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
(3)
Recommend solder paste is Type 3 or Type 4.
(4)
For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5)
Solder mask thickness should be less than 20
m on top of the copper circuit pattern
(6)
Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically etched stencils results in
inferior solder paste volume control.
(7)
Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to
solder wetting forces.
Place all the external components very close to the TPA2051D3. Placing the decoupling capacitor, Cs, close to
the TPA2051D3 is important for the efficiency of the Class-D amplifier. Any resistance or inductance in the trace
between the device and the capacitor can cause a loss in efficiency.
Recommended trace width at the solder balls is 75-
m to 100-m to prevent solder wicking onto wider PCB
traces.
For high current pins (PVDD, PGND, and audio output pins) of the TPA2051D3, use 100-
m trace widths at the
solder balls and at least 500-
m PCB traces to ensure proper performance and output power for the device.
For the remaining signals of the TPA2051D3, use 75-
m to 100-m trace widths at the solder balls. The audio
input pins (INR± and INL±) must run side-by-side to maximize common-mode noise cancellation.
The maximum ambient temperature depends on the heat-sinking ability of the PCB system. The derating factor
for the packages are shown in the dissipation rating table. Converting this to
θ
JA for the WCSP package:
Given
θ
JA of 148°C/W, the maximum allowable junction temperature of 150°C, and the internal dissipation of
0.2 W for 2 W, 8
load, 5 V supply, the maximum ambient temperature can be calculated with
Equation 4.Equation 4 shows that the calculated maximum ambient temperature is 120°C at maximum power dissipation
with a 5 V supply and 8
a load. The TPA2051D3 is designed with thermal protection that turns the device off
when the junction temperature surpasses 150°C to prevent damage to the IC.
In using Class-D amplifiers with CODECs and DACs, sometimes there is an increase in the output noise floor
from the audio amplifier. This occurs when mixing of the output frequencies of the CODEC/DAC mix with the
switching frequencies of the audio amplifier input stage. The noise increase can be solved by placing a low-pass
filter between the CODEC/DAC and audio amplifier. This filters off the high frequencies that cause the problem
and allow proper performance. See
Figure 42 for the application diagram.
Copyright 2009, Texas Instruments Incorporated
27