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參數資料
| 型號： | TPA2051D3YFFR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2.9 W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA25 |
| 封裝： | 2.16 X 2.11 MM, 0.40 MM PITCH, GREEN, WCSP-25 |
| 文件頁數： | 6/34頁 |
| 文件大小： | 1594K |
| 代理商： | TPA2051D3YFFR |
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APPLICATION CIRCUIT
+
–
MONO
OUT-
OUT+
Mixer
+
Mode
Control
+
AGC
PVDD
1 F
INL1
HPLEFT
HPRIGHT
-66dB to +18dB
Volume Control
SDA
-66dB to +18dB
Volume Control
-66dB to +18dB
Volume Control
I2C Interface
SCL
MONO+
VDD
VSS
VDD
VSS
Voice-Mode
Bypass
Voice-Mode
Bypass
INR1
INL2
INR2
EN
Gain
Select
-12dB
to
0dB
1.5dB/
step
VDD
PGND
PWM
H-
Bridge
DVDD
BYPASS-
BYPASS+
Bias Control
and Pop
Suppression
Charge
Pump
1 F
2.2 F
CPP
CPN
HPVSS
PGND
1 F
VREF
2.2 F
HPVDD
AGND
Gain
Select:
+12 dB
+6 dB
FM Tuner
CODEC
8
Dual-Mode
Speaker
Stereo
Headphone
Jack
ABB
9.1
1 F
DBB
1 F
VBATT
AVDD
1 F
VBATT
TPA2051D3
GENERAL I
2C OPERATION
Register(N)
8-BitDatafor
Register(N+1)
SLOS641A – JUNE 2009 – REVISED OCTOBER 2009 ..................................................................................................................................................... www.ti.com
Figure 33. Typical Apps Configuration with Differential Input Signals
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially one bit at a time. The address and data 8-bit bytes are transferred most
significant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions bust occur within
the low time of the clock period. Figure 34 shows a typical sequence. The master generates the 7-bit slave
address and the read/write (R/W) bit to open communication with another device and then waits for an
acknowledge condition. The TPA2051D3 holds SDA low during the acknowledge clock period to indicate
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection.
The TPA2051D3 operates as an I2C slave. The I2C voltage can not exceed the TPA2051D3 supply voltage,
AVDD.
An external pull-up resistor must be used for the SDA and SCL signals to set the logic high level for the bus.
When the bus level is 3.3 V, use pull-up resistors between 660
and 1.2 k.
Figure 34. Typical I2C Sequence
14
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2051D3
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相關代理商/技術參數 |
參數描述 |
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| TPA2051D3YFFT | 功能描述:音頻放大器 2.9W 3-Input Audio Subsystem RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TPA2054D4A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1.4 W/CH STEREO CLASS-D AUDIO SUBSYSTEM WITH DirectPatha?￠ HEADPHONE AMPLIFIER AND 3:1 INPUT MUX |
| TPA2054D4AYZKR | 功能描述:音頻放大器 1.4 W/Ch 3-Inp Audio Subsystem RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TPA2054D4AYZKT | 功能描述:音頻放大器 1.4 W/Ch 3-Inp Audio Subsystem RoHS:否 制造商:STMicroelectronics 產品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TPA2054D4YZKEVM | 功能描述:音頻 IC 開發工具 TPA2054D4YZKEVM Eval Mod RoHS:否 制造商:Texas Instruments 產品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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