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參數資料
型號: TPA2054D4AYZKR
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻/視頻放大
英文描述: 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25
封裝: 2.61 X 2.61 MM, GREEN, DSBGA-25
文件頁數: 8/30頁
文件大小: 858K
代理商: TPA2054D4AYZKR
SLOS666 – MAY 2010
www.ti.com
SINGLE-BYTE WRITE
As shown in Figure 43, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TPA2054D4A responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA2054D4A internal memory address being accessed. After
receiving the register byte, the TPA2054D4A again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data write transfer.
Figure 43. Single-Byte Write Transfer
MULTI-BYTE WRITE AND INCREMENTAL MULTI-BYTE WRITER
A multiple-byte data write transfer is identical to a single-byte data write transfer with the exception that multiple
data bytes are transmitted by the master device to the TPA2054D4A as shown in Figure 44. After receiving each
data byte, the TPA2054D4A responds with an acknowledge bit.
Figure 44. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As shown in Figure 45, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA2054D4A address and the read/write bit, the TPA2054D4A responds with an
acknowledge bit. The master then sends the internal memory address byte, after which the TPA2054D4A issues
an acknowledge bit. The master device transmits another start condition followed by the TPA2054D4A address
and the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the
TPA2054D4A transmits the data byte from the memory address being read. After receiving the data byte, the
master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read
transfer.
Figure 45. Single-Byte Read Transfer
16
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPA2054D4A
相關PDF資料
PDF描述
TPA2054D4AYZKT 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25
TPA2054D4YZKR 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25
TPA2054D4YZKT 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25
TPA2100P1YZHR 1 CHANNEL, AUDIO AMPLIFIER, PBGA16
TPA2100P1YZHT 1 CHANNEL, AUDIO AMPLIFIER, PBGA16
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