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參數(shù)資料
| 型號： | TPA2054D4YZKR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25 |
| 封裝： | 2.61 X 2.61 MM, GREEN, DSBGA-25 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 949K |
| 代理商： | TPA2054D4YZKR |
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DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
TIMING CHARACTERISTICS
www.ti.com ..................................................................................................................................................................................................... SLOS607 – APRIL 2009
PACKAGE
TA < 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
YZK (WCSP)
1.12 W
9 mW/°C
720 mW
585 mW
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Class-D supply voltage, PVDD
2.5
5.5
V
Charge pump supply voltage, VDDHP
2.5
5.5
V
I2C supply voltage, DVDD
1.7
3.3
V
VIH
High-level input voltage
SDA, SCL, RESET, DVDD = 1.8 V
1.3
V
SDA, SCL, RESET, DVDD = 3.3 V
3.0
VIL
Low-level input voltage
SDA, SCL, RESET, DVDD = 1.8 V
0.3
V
SDA, SCL, RESET, DVDD = 3.3 V
TA
Operation free-air temperature
–40
85
°C
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Power supply rejection ratio
VDD = 2.5 V to 5.5 V, Single-ended mode
48
75
dB
(Class-D amplifiers)
DC Power supply rejection ratio
VDD = 2.5 V to 5.5 V, Single-ended mode
60
80
dB
(headphone amplifiers)
High-level input current (SDA, SCL,
1
A
RESET)
Low-level input current (SDA, SCL,
1
A
RESET)
Supply current
VDD = 5.5 V, Class-D and Headphone amplifiers active, no load
15.8
20
mA
VDD = 4.2 V, Class-D active, Headphone deactivated, no load
7.5
10.5
mA
VDD = 4.2 V, Headphone active, Class-D deactivated, no load
10
13.5
mA
VDD = 2.5 V to 5.5 V, SWS=1 or RESET ≤ 0.3 V (shutdown mode)
0.15
2
A
For I
2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLN
Frequency, SCL
No wait states
400
kHz
tW(H)
Pulse duration, SCL high
0.6
s
tW(L)
Pulse duration, SCL low
1.3
s
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start condition
1.3
s
tsu2
Setup time, SCL to start condition
0.6
s
th2
Hold time, start condition to SCL
0.6
s
tsu3
Setup time, SCL to stop condition
0.6
s
Copyright 2009, Texas Instruments Incorporated
5
Product Folder Link(s): TPA2054D4
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