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TPS23841
SLUS745–NOVEMBER 2006
TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
DESCRIPTION
NAME
PAP
PJD
POWER AND GROUND
48-V input to the device. This supply can have a range of 22 V to 57 V. This pin should be decoupled
with a 0.1-
μ
F capacitor from V48 to AG1 placed as close to the device as possible.
10-V analog supply. The 10-V reference is generated internally and connects to the main internal
analog power bus. A 0.1-
μ
F de-coupling capacitor should terminate as close to this node and the
AG1 pin as possible. Do not use for an external supply.
6.3-V analog supply. A 0.1-
μ
F de-coupling capacitor should terminate as close to this pin and the
AG1 pin as possible. Do not use for an external supply.
3.3-V logic supply. The 3.3-V supply is generated internally and connects to the internal logic power
bus. A 0.1-
μ
ìF de-coupling capacitor should terminate as close to this node and the DG pin as
possible. This output can be used as a low current supply to external logic.
2.5-V reference supply. The V2.5 is generated internally and connects to the internal reference power
bus. This pin should not be tied to any external supplies. A 0.1-
μ
F de-coupling capacitor should
terminate as close to this node and the RG pin as possible. Do not use for an external supply.
Analog ground 1. This is the analog ground of the V6.3, V10 and V48 power systems. It should be
GND externally tied to the common copper 48-V return plane. This pin should carry the low side of three
de-coupling capacitors tied to V48, V10 and V6.3.
Analog ground 2. This is the analog ground which ties to the substrate and ESD structures of the
GND device. It should be externally tied to the common copper 48-V return plane. AG1 and AG2 must be
tied together directly for the best noise immunity.
Digital ground. This pin connects to the internal logic ground bus. It should be externally tied to the
GND
common copper 48-V return plane.
Reference ground. This is a precision sense of the external ground plane. The integration capacitor
(CINT) and the biasing resistor (RBIAS pin) should be tied to this ground. This ground should also be
GND
used to form a printed wiring board ground guard ring around the active node of the integration
capacitor (CINT). It should tie to common copper 48-V return plane.
V48
60
5
I
V10
58
7
O
V6.3
59
6
O
V3.3
24
41
O
V2.5
54
11
O
AG1
57
8
AG2
61
4
DG
23
42
RG
56
9
PORT ANALOG SIGNAL
P1
P2
P3
P4
N1
N2
N3
N4
RET1
RET2
RET3
RET4
CINT1
CINT2
CINT3
CINT4
7
10
39
42
6
11
38
43
5
12
37
44
4
13
36
45
58
55
26
23
59
54
27
22
60
53
28
21
61
52
29
20
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Port Positive. 48-V load sense pin. Terminal voltage is monitored and controlled differentially with
respect to each Port N pin Optionally, if the application warrants, this high side path can be protected
with the use of a self resetting poly fuse.
Port negative. 48-V load return pin. The low side of the load is switched and protected by internal
circuitry that will limit the current.
48 V return pin
Integration capacitor. This capacitor is used for the ramp A/D converter signal integration. Connect A
0.027-
μ
F capacitor from this pin to RG. To minimize errors use a polycarbonate, poly-polypropylene,
polystyrene or teflon capacitor type to prevent leakage. Other types of capacitors can be used with
increased conversion error.
8
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