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參數資料
型號: TPS2481PW
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: POWER SUPPLY SUPPORT CKT, PDSO20
封裝: GREEN, PLASTIC, TSSOP-20
文件頁數: 21/56頁
文件大小: 1381K
代理商: TPS2481PW
SLUS939B – APRIL 2010 – REVISED DECEMBER 2010
www.ti.com
Power, Current, and Voltage Monitoring (PIV)
The TPS2480/81 digital current-shunt monitor has an I2C / SMBus-compatible interface. It provides digital
current,
voltage,
and
power
readings
for
accurate
decision-making
in
precisely-controlled
systems.
Programmable registers allow flexible configuration for measurement resolution, and continuous versus-triggered
operation. Detailed register information appears in the Register Information Section. See the Register Block
Diagram for a block diagram of the TPS2480 / 81 PIV monitoring circuits.
PIV Monitoring - Typical Application Circuit Considerations
Figure 17 shows a typical application circuit for the TPS2480/81. 0.1-mF ceramic capacitors must be placed as
close as possible to the supply and ground pins for supply bypassing.
The pull-up resistors shown on the SDA and SCL lines are not needed if there are pull-up resistors on these
same lines elsewhere in the system. Resistor values shown are typical: consult the I2C or SMBus specification to
determine acceptable values.
I
2C Bus Overview
The I2C and SMBus protocols are essentially compatible with each other and the TPS2480/81 are compatible
with both. This allows use of the I2C interface throughout this data sheet as the primary example, with SMBus
protocol specified only when there is a difference.
Two bidirectional lines, SCL and SDA, connect the TPS2480 / 81 to the bus. Both SCL and SDA are open-drain
connections. The device that initiates the transfer is called a master, and the devices controlled by the master
are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls, the
bus access, and generates START and STOP conditions.
To address a specific device, the master initiates a START condition by pulling SDA from a HIGH to a LOW logic
level while SCL is HIGH. All slaves on the bus shift in the slave address byte on the rising edge of SCL, with the
last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being
addressed responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data
transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH is interpreted as a
START or STOP condition.
Once all data have been transferred, the master generates a STOP condition, indicated by pulling SDA from
LOW to HIGH while SCL is HIGH. The TPS2480/81 includes a 28-ms timeout on its interface to prevent locking
up an SMBus.
28
Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2480 TPS2481
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相關代理商/技術參數
參數描述
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