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參數資料
| 型號： | TPS3610U18PWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 5.10 X 6.60 MM, GREEN, PLASTIC, TSSOP-14 |
| 文件頁數： | 24/26頁 |
| 文件大小： | 711K |
| 代理商： | TPS3610U18PWG4 |
TPS3610U18, TPS3610T50
BATTERY BACKUP SUPERVISORS FOR RAM RETENTION
SLVS327B – DECEMBER 2000 – REVISED DECEMBER 2002
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
chip-enable signal gating
The internal gating of chip-enable signals, CE, prevents erroneous data from corrupting CMOS RAM during an
undervoltage condition. The TPS3610 use a series transmission gate from CEIN to CEOUT. During normal
operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions. When reset
is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short
CE propagation delay from CEIN to CEOUT enables TPS3610 devices to be used with most processors.
The CE transmission gate is disabled and CEIN is high-impedance (disable mode) while reset is asserted.
During a power-down sequence, when VDD crosses the reset threshold, the CE transmission gate is disabled
and CEIN immediately becomes high impedance if the voltage at CEIN is high. If CEIN is low while reset is
asserted, the CE transmission gate is disabled at the same time CEIN goes high, or 15
s after RESET asserts,
whichever occurs first. This allows the current write cycle to complete during power-down. When the CE
transmission gate is enabled, the impedance of CEIN appears as a resistor in series with the load at CEOUT.
The overall device propagation delay through the CE transmission gate depends on VOUT, the source
impedance of the device connected to CEIN and the load at CEOUT. To achieve minimum propagation delay,
the capacitive load at CEOUT should be minimized, and a low-output-impedance driver should be used.
During disable mode, the transmission gate is off and an active pullup connects CEOUT to VOUT. The pullup
turns off when the transmission gate is enabled.
15
s
CEIN
CEOUT
RESET
t
Figure 2. Chip-Enable Timing
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相關代理商/技術參數 |
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| TPS3610U18PWR | 功能描述:監控電路 Battery-Backup for RAM Retention RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3610U18PWRG4 | 功能描述:監控電路 Battery-Backup for RAM Retention RoHS:否 制造商:STMicroelectronics 監測電壓數: 監測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TPS3610U25PWR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TPS3610U30PWR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TPS3610U33PWR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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