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參數資料
| 型號： | TPS40022PWP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 0.01 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | POWERPAD, PLASTIC, HTSSOP-16 |
| 文件頁數： | 26/29頁 |
| 文件大小： | 337K |
| 代理商： | TPS40022PWP |
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TPS40020
TPS40021
TPS40022
SLUS535 – MARCH 2003
www.ti.com
6
ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 85°C, TJ = TA, VDD = 5.0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNCHRONIZATION
VENSY Synchronization enable low threshold voltage
0.7
VBLNK
Synchronization current limit enable threshold
voltage
Referenced to VDD
–0.7
V
tMIN
Minimum synchronization input pulse width
50
35
ns
PREDICTIVE DELAY
VSWP
Sense voltage to modulate delay time
–350
mV
t
Maximum delay modulation
LDRV OFF-to-HDRV ON
40
65
90
tLDHD
Counter delay/bit time
LDRV OFF-to-HDRV ON
3.0
4.5
6.2
ns
t
Maximum delay modulation
HDRV OFF-to-LDRV ON
35
60
85
ns
tHDLD
Counter delay/bit time
HDRV OFF-to-LDRV ON
2.4
4.0
5.6
RECTIFIER ZERO CURRENT COMPARATOR
VSW
Sense voltage to turn off
rectifier MOSFET
TPS40020
TPS40022
LDRV output = OFF
–5
–2.5
2
mV
tZBLNK Zero current blanking time(1)
150
ns
(1) Ensured by design. Not production tested.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
BOOT1
16
I
This pin provides a bootstrapped supply for the high side FET driver, enabling the gate of the high side FET to be
driven above the input supply rail. Connect a capacitor from this pin to the SW pin.
BOOT2
13
I
This pin provides a secondary bootstrapping necessary for generation of PVDD. Connect a capacitor from this
pin to SW.
COMP
5
O
Output of the error amplifier. Refer to Electrical Characteristics table for loading constraints.
FB
4
I
Inverting input of the error amplifier. In normal operation, VFB is equal to the internal reference level of 700 mV.
HDRV
15
O
The gate drive output for the high side N-channel MOSFET switch is bootstrapped to near PVDD for good
enhancement of the high-side switch. The HDRV switches from BOOT1 to SW.
ILIM/SYNC
1
I
The current limit pin is used to set the current limit threshold. A current sink from this pin to GND sets the threshold
voltage for overcurrent across a resistor connected to VDD. Synchronization is accomplished by pulling IMAX to
less than 1 V for a period greater than the minimum pulse width and then releasing. An open collector or drain
device should be used. These pulses must be of higher frequency than the free running frequency of the local
oscillator.
LDRV
11
O
Gate drive output for the low-side synchronous rectifier N-channel MOSFET. LDRV switches from PVDD to
PGND.
OSNS
3
O
The output sense pin is connected to a resistor divider from VOUT to GND (identical to the main feedback loop)
and is used to sense power good condition and provides reference for the transient comparators.
PGND
9
O
Power (high-current) ground used by LDRV.
PWRGD
10
–
Power good. This is an open-drain output which connects to the supply via an external resistor.
PVDD
12
O
This pin is the regulated output of the charge-pump and provides the supply voltage for the LDRV driver stage.
PVDD also drives the bootstrap circuit which generates the voltage on BOOT1.
RT
7
I
External pin for programming the oscillator frequency.
SGND
8
–
Signal ground
SS/SD
6
I
The soft-start/shutdown pin provides user programmable soft-start timing and shutdown capability for the
controller.
SW
14
I
This pin, used for overcurrent, zero-current, and in the anti-cross conduction sensing is connected to the switched
node on the converter. Overcurrent is detected by sensing the voltage at this pin with respect to VDD while the
high-side switch is on. Zero current is detected by sensing the pin voltage with respect to ground when the low-side
rectifier MOSFET is on.
VDD
2
I
Power input for the device. Maximum voltage is 5.5 V. De-coupling of this pin is required.
PRODUCT
PREVIEW
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