
SGLS310B – JULY 2005 – REVISED OCTOBER 2010
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DEVICE INFORMATION
(1)
For more information on the PWP package, see the Texas Instruments Technical Brief (
SLMA002)
(2)
PowerPAD heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input
BOOST
14
O
voltage. A 0.1-F ceramic capacitor should be connected from this pin to the drain of the lower MOSFET.
5-V reference. This pin should be bypassed to ground with a 0.1-F ceramic capacitor. This pin may be used
BP5
3
O
with an external dc load of 1 mA or less.
10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a
BP10
11
O
1-F ceramic capacitor. This pin may be used with an external dc load of 1 mA or less.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to
COMP
8
O
the VFB pin to compensate the overall loop. The COMP pin is internally clamped above the peak of the ramp to
improve large signal transient response.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
HDRV
13
O
(MOSFET off).
Current limit pin used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
ILIM
16
I
voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared to
the voltage drop (VIN -SW) across the high side MOSFET during conduction.
A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into
KFF
1
I
this pin is internally divided and used to control the slope of the PWM ramp.
Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
LDRV
10
O
(MOSFET off).
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of
PGND
9
–
the lower MOSFET(s).
RT
2
I
A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
SGND
5
–
Signal ground reference for the device
Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 A. The resulting voltage ramp on the SS pin is used
as a second non-inverting input to the error amplifier. The output voltage begins to rise when VSS/SD is
approximately 0.85 V. The output continues to rise and reaches regulation when VSS/SD is approximately
SS/SD
6
I
1.55 V. The controller is considered shut down when VSS/SD is 125 mV or less. All internal circuitry is inactive.
The internal circuitry is enabled when VSS/SD is 210 mV or greater. When VSS/SD is less than approximately
0.85 V, the outputs cease switching and the output voltage (VOUT) decays while the internal circuitry remains
active.
SW
12
I
This pin is connected to the switched node of the converter and used for overcurrent sensing.
Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master
SYNC
4
I
frequency. If synchronization is not used, connect this pin to SGND.
6
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