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參數資料
| 型號： | TPS40077PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | 2 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數： | 24/43頁 |
| 文件大小： | 847K |
| 代理商： | TPS40077PWPRG4 |
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CBOOST u
Q
g(TOTAL)
DVBOOST
(43)
Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
K
PWM ^
V
UVLO
1 V
(44)
K
LC +
1 ) s
ESR
COUT
1 ) s
LOUT
ROUT
) s
2
LOUT
COUT
(45)
Gc(s) + KPWM
K
LC
V
UVLO
1 V
1 ) s
ESR
COUT
1 ) s
LOUT
ROUT
) s
2
LOUT
COUT
(46)
DCGAIN + 20
log
V
UVLO
V
RAMP
+ 20
log(7) + 16.9 dB
(47)
f
LC_Pole +
1
2p
LOUT
COUT
+ 4.3 kHz
(48)
f
ESR_Zero +
1
2p
ESR
COUT
+ 2.1 kHz
(49)
SLUS714D – JANUARY 2007 – REVISED APRIL 2009 ..................................................................................................................................................... www.ti.com
The total gate charge of the switching MOSFET is 23 nC. A minimum CBOOST of 0.092
F is required. A 0.1 F
capacitor was chosen. This capacitor must be able to withstand the maximum input voltage plus the maximum
voltage on DBP. This is 13.2 V plus 9.0 V, which is 22.2 V. A 50-V capacitor is used.
To reduce losses in the TPS40077 and to increase the available gate voltage for the switching MOSFET, an
external diode can be added between the DBP pin and the BOOST pin of the IC. A small-signal Schottky diode
should be used here, such as the BAT54.
A graphical method is used to select the compensation components. This is a standard feed-forward buck
converter. Its PWM gain is given by Equation 44.
The ramp voltage is 1 V at the UVLO voltage. Because of the feed-forward compensation, the programmed
UVLO voltage is the voltage that sets the PWM gain.
The gain of the output LC filter is given by Equation 45.
The PWM and LC gain is
To plot this on a Bode plot, the dc gain must be expressed in dB. The dc gain is equal to KPWM. To express this
in dB, take its logarithm and multiply by 20. For this converter, the dc gain is
Also, the pole and zero frequencies should be calculated. A double pole is associated with the LC and a zero is
associated with the ESR of the output capacitor. The frequencies where these occur can be calculated using
equations,
These are shown in the Bode plot of Figure 31.
30
Copyright 2007–2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS40077
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