
TPS51020
SLUS564C JULY 2003 REVISED OCTOBER 2008
10
www.ti.com
APPLICATION INFORMATION
PWM OPERATION
The PWM control block utilizes a fixed-frequency, feed-forward, voltage-mode control scheme with a
wide-bandwidth, low-impedance output error amplifier as the voltage servo control block. This scheme allows
the highest efficiency down conversion while maintaining excellent line regulation and fast transient response.
Loop compensation is programmed by connecting a filter network between the COMPx pin and the INVx pin.
The wide bandwidth error amplifier handles conventional Type II compensation or Type III compensation when
using ceramic capacitors for the converter output. For channel one, the reference signal for the control loop is
always a precision 0.85-V internal reference, while the channel two loop reference is either the 0.85-V reference
or, in the case of DDR mode, one half the VO1_VDDQ voltage, (VO1_VDDQ)/2. The output signal of the error
amplifier appears at the COMPx pin and is compared to a buffered version of the 0.6-V oscillator ramp. When
TRIP2 pin is tied to VIN through a resistor, the voltage ramp is further modulated by the input voltage, VIN, to
maintain a constant modulator gain. If the TRIP2 pin is connected to ground through a resistor, then the voltage
ramp remains fixed regardless of VIN value.
The oscillator frequency is internally fixed and can be selected at 270 kHz, 360 kHz or 470 kHz by insertion of
a clamping resistor on the SSTRTx pin per Table 1. For example, 470 kHz can be attained when both SSTRTx
voltages exceed 3.5 V, as described in WAVEFORM1. The controller begins with 270 kHz in the first stage of
the softstart, and then increases to 470 kHz at the steady state. When 270 kHz is selected, both of SSTRTx
voltages are kept below 3.5 V so that the frequency is the same 270 kHz for the entire operation.
Two channels are operated in 180 degrees out-of-phase interleave switching mode. This interleaving helps
reduce the input current ripple requirement for the input capacitor. However, because the PWM loop determines
both the turn-off AND turn-on of the high-side MOSFET, this 180 degree operation may not be apparent by
looking at the LLx nodes only. Rather, the turn-off cycle of one channel always corresponds to the turn-on cycle
of the other channel and vise-versa. As a result, input ripple is reduced and dynamic response is improved over
a broad input voltage range.
MAXIMUM DUTY CYCLE
Because most notebook applications typically run from three to four cell LiIon or run from a 20-V adapter, 100%
duty cycle operation is not required. Rather, the TPS51020 is optimized for low duty ratio step-down conversion.
As a result of limiting the duty cycle, the flying BST capacitor is refreshed reliably and the low-side over current
detection circuitry is capable of detecting an overcurrent condition even if the output is stuck between the
regulation point and UVP. The maximum duty cycle for each operating frequency is 88% for 270 kHz, 85% for
360 kHz and 82% for 470 kHz.
It should be noted that if the system is operating close to maximum (or minimum) duty cycle, it may be difficult
for the converter to respond quickly during line/load transients or state changes (such as frequency switching
during soft start or PWM to SKIP mode transitions). This slow response is due to the dynamic range of the COMP
pin and is usually not a result of poor phase compensation. In the case of minimum duty cycle operation, the
slow response is due to the minimum pulse width of the converter (100 ns TYP). In this case (counter intuitively),
it may be advisable to slow down the switching frequency of the converter in order to improve response time.