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參數資料
| 型號： | TPS51315RGFR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩壓器 |
| 英文描述： | SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PQCC40 |
| 封裝： | GREEN, PLASTIC, QFN-40 |
| 文件頁數： | 29/32頁 |
| 文件大小： | 1028K |
| 代理商： | TPS51315RGFR |
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SLUS881A
– MAY 2009 – REVISED MAY 2011
PIN DESCRIPTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
Enable/power-save pin. Connect to ground to disable switched-mode power supply (SMPS ). Connect to 3.3
EN_PSV
34
I
V or 5 V to turn on SMPS and enable skip mode. Float to turn on SMPS but disable skip mode (forced
continuous conduction mode).
1
GND
2
I
Signal ground pin.
4
16
17
18
19
20
21
Source node of the high-side power FET and drain node of the low-side power FET. Connect this pin to
LL
22
I/O
output inductor.
23
24
25
26
27
28
29
NC
—
No connection inside. Leave open.
33
3
5
6
PGND
7
I/O
Power GND. Source node of the low-side power FET.
8
9
10
Power-good window comparator: open drain output. Pull up to 5-V rail with a pull-up resistor. Current
PGOOD
40
O
capability is 7.5 mA.
TON
35
I
On-time / frequency adjustment pin. Connect to LL with proper resistor to program switching frequency.
Overcurrent trip point set input. Connect resistor from this pin to signal ground to set threshold for both
TRIP
32
I
overcurrent and negative overcurrent limit.
5-V power supply input for all control circuitry except gate drivers. Apply an R-C filter to reject high-frequency
V5FILT
38
I
switching noise.
5-V Power supply input for FET gate drivers. Internally connected to VBST by a PN diode. Connect a cpacitor
V5IN
31
I
with a value of 1
μF or greater between this pin and PGND to support instantaneous current for gate drivers.
Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL-node. An
VBST
30
I
internal PN diode is connected between V5IN to this pin. Add an external schottky diode if forward drop is
critical to ensure efficient operation.
VFB
39
I
SMPS voltage feedback input. Connect the resistor divider here for adjustable output.
11
12
VIN
13
I
Input power source. Drain node of the high-side power FET.
14
15
VOUT
36
I
Connect to SMPS output. This terminal serves as the output voltage monitor for on-time adjustment.
VOUT_DS
37
O
Prebias start-up and selectable output discharge. It is also the input for the output discharge switch.
6
Copyright
2009–2011, Texas Instruments Incorporated
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